CS5535 datasheet(137/555 Pages) NSC

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LPC Port Functional Description (Continued)

4.13.2 Cycle Protocol

Start of Cycle (see Figure 4-39): The host asserts

LFRAME# for one or more clocks and drives a START

value on LAD[3:0], all peripherals stop driving the LAD[3:0]

signals even if in the middle of a transfer. The peripheral

must always use the last START value when LFRAME#

was active. On the clock after the START value, the host

de-asserts LFRAME#.

Abort Mechanism (see Figure 4-40): The host can cause

an abort on the LPC interface by driving LFRAME# active

with a START value of 1111b. The host must keep

LFRAME# active for at least four consecutive clocks and

drive LAD[3:0] to 1111b no later than the fourth clock after

LFRAME# goes active. The host must drive LFRAME#

inactive for at least one clock after an abort.

An abort typically occurs on SYNC timeouts.

Figure 4-39. Start of Cycle Timing Diagram

Figure 4-40. Abort Mechanism Timing Diagram

SYNC

1-N

Sync: Allows peripheral or host to synchronize (add wait-states). Generally, the peripheral or

host drives 0101 or 0110 until no more wait-states are needed. At that point it will drive 0000. All

other combinations are reserved.

0000

Sync achieved with no error.

DMA.

Sync achieved with no error. Also indicates no more transfer desired for that chan-

nel, and DMA request is de-asserted.

0101

Indicates that Sync not achieved yet, but the part is driving the bus.

DMA. Part indicating wait states.

0110

Indicates that Sync not achieved yet, but the part is driving the bus, and expect long

Sync.

DMA. Part indicating wait states, and many wait states will be added.

1010

Special case. Peripheral indicating errors, see sync section in protocol overview.

DMA. Sync achieved with error. Also indicates no more transfers desired for that chan-

nel, and DMA request is de-asserted.

1001

DMA (only). Sync achieved with no error and more DMA transfer desired to continue

after this transfer.

Table 4-23. Cycle Field Definitions: Target Memory, I/O, and DMA (Continued)

Field

# Clocks

Comment

START CYCTYP

LCLK

LAD[3:0]#

LFRAME#

ADDR

TAR

SYNC

DATA

START

TAR

1 - 8

1 - n

START CYCTYP

LCLK

LAD[3:0]#

LFRAME#

ADDR

TAR

SYNC

11 - 8

Too many

Syncs causes

Timeout

Peripheral must

Stop driving

Chip set will

drive high

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