CS5535 datasheet(134/555 Pages) NSC

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134

Revision 0.8

4.13 LOW PIN COUNT PORT

The Low Pin Count port is based on Intel’s Low Pin Count

(LPC) Interface Specification v1.0. In addition to the

required pins, the CS5535 also supports two optional pins:

LDRQ# and SERIRQ. The LPC interface supports memory,

I/O, DMA, and Intel’s Firmware Hub Interface. Figure 4-38

shows the block diagram of the LPC port.

Features

• Based on Intel’s Low Pin Count (LPC) Specification

v1.0.

• Serial IRQ support.

• Supports memory, I/O, and DMA cycle types.

• Bus master cycles not supported.

• CLKRUN# and LPCPD# not supported. SMI# and PME#

supported via GPIOs.

• On-chip DMA transfers through LPC.

• Supports Intel’s FirmWare Hub (FWH) Interface:

— 5 Signal communication interface supporting byte-at-

a-time reads and writes.

— LAD[3:0] called as FWH0-FWH3 and LFRAME# as

FWH4.

Figure 4-38. LPC Block Diagram

GeodeLink Adapter

Local Bus

Local Bus Slave

Local Bus Master

LPC Master

DRQ

LDRQ

SIRQ

LPC Reg

To PIC

LFRAME#

LDRQ#

LAD[3:0]

SERIRQ

To DMA

From DMA

LPC to/from Local Bus

Busy

LPC Master

Initiates all transactions on LPC bus, takes/issues requests from Local bus.

Local Bus Master

Takes request from LPC master and DMA.

Local Bus Slave

Issues request to LPC master from Local bus.

SIRQ

Decodes SERIRQ into IRQ to be passed on to PIC.

LDRQ

Decodes LDRQ# into DRQ sets and clears.

DRQ

Combines multiple LDRQ# outputs and passes results to DMA.

LPC Reg

Contains all the LPC I/O registers.

LPC to/from Local Bus

LPC to Local bus interface module.

Busy

Generates busy signal for clock controls.

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