CS5535 datasheet(268/555 Pages) NSC

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268

Revision 0.8

USB Register Descriptions (Continued)

5.5.1.5

GeodeLink Device Power Management MSR (USBC_GLD_MSR_PM)

SYS_ERR_EN

System Error Enable. Write 1 to enable SYS_ERR_FLAG (bit 42) and to allow the

event to generate an ERR.

PARIN_ERR_EN

Parity Error In Enable. Write 1 to enable PARIN_ERR_FLAG (bit 41) and to allow the

event to generate an ERR.

PAROUT_ERR_

Parity Error Out Enable. Write 1 to enable PAROUT_ERR_FLAG (bit 40) and to allow

the event to generate an ERR.

TIMEOUT_ERR_

Timeout Error Enable. Write 1 to enable TIMEOUT_ERR_FLAG (bit 39) and to allow

the event to generate an ERR.

PA_SVADRS_

ERR_EN

PCI Adapter Slave Interface Address Parity Error Enable. Write 1 to enable

PA_SVADRS_ERR_FLAG (bit 38) and to allow the event to generate an ERR.

PA_TABORT_

ERR_EN

PCI Adapter Target Abort Error Enable. Write 1 to enable PA_TABORT_ERR_FLAG

(bit 37) and to allow the event to generate an ERR.

PA_MABORT_ER

R_EN

PCI Adapter Master Abort Error Enable. Write 1 to enable

PA_MABORT_ERR_FLAG (bit 36) and to allow the event to generate an ERR.

EXCEP_ERR_EN

Exception Bit Error Enable. Write 1 to enable EXCEP_ERR_FLAG (bit 35) and to

allow the event to generate an ERR.

2:1

RSVD

Reserved. Writes don’t care. Reads return zero.

UNEXP_TYPE_

ERR_EN

Unexpected Type Error Enable. Write 1 to enable UNEXP_TYPE_ERR_FLAG (bit

32) and to allow the event to generate an ERR.

MSR Address

USBC1: 51600004h

USBC2: 51200004h

Type

R/W

Reset Value

00000000_00000000h

USBC_GLD_MSR_ERROR Bit Descriptions (Continued)

Bit

Name

Description

USBC_GLD_MSR_PM Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RSVD

PMODE

USBC_GLD_MSR_PM Bit Descriptions

Bit

Name

Description

63:6

RSVD

Reserved. Returns 0 on read.

5:4

PMODE2

Power Mode 2. Controls clock behavior for the USB Core.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

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