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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FXPS7115D4S датащи(PDF) 56 Page - NXP Semiconductors |
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FXPS7115D4S датащи(HTML) 56 Page - NXP Semiconductors |
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56 / 72 page  NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa VCC_min ≤ (VCC – VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified. Symbol Parameter Condition Min Typ Max Units tLEAD Serial interface timing[3] SS_B asserted to SCLK high (SS_B = 10 % of VCC to SCLK = 10 % of VCC) [1] — 50 — ns tACCESS Serial interface timing[3] SS_B asserted to SCLK high (SS_B = 10 % of VCC to MISO = 10/90 % of VCC) [1] — — 50 ns tSETUP Serial interface timing[3] SS_B asserted to SCLK high (MOSI = 10/90 % of VCC to SCLK = 10 % of VCC) [1] — 20 — ns tHOLD_IN MOSI data hold time (SCLK = 90 % of VCC to MOSI = 10/90 % of VCC) [1] — 10 — ns tHOLD_OUT Serial interface timing[3] MOSI data hold time (SCLK = 90 % of VCC to MISO = 10/90 % of VCC) [1] 0 — — ns tVALID Serial interface timing[3] SCLK low to data valid (SCLK = 10 % of VCC to MISO = 10/90 % of VCC) [1] — — 30 ns tLAG Serial interface timing[3] SCLK low to SS_B high (SCLK = 10 % of VCC to SS_B = 90 % of VCC) [1] — 60 — ns tDISABLE Serial interface timing[3] SS_B high to MISO disable (SS_B = 90 % of VCC to MISO = Hi Z) [1] — — 60 ns tSSN Serial interface timing[3] SS_B high to SS_B low (SS_B = 90 % of VCC to SS_B = 90 % of VCC) [1] — 500 — ns tSLKSS Serial interface timing[3] SCLK low to SS_B low (SCLK = 10 % of VCC to SS_B = 90 % of VCC) [1] — 50 — ns tSSCLK Serial interface timing[3] SS_B high to SCLK high (SS_B = 90 % of VCC to SCLK = 90 % of VCC) [1] — 50 — ns tLAT_SPI Data latency — — 1 ns Signal chain tSigChain Signal chain sample time [4] — 48 — μs fc0 Cutoff frequency, filter option #0, 4-pole [2] [4] — 800 — Hz fc1 PABS low-pass filter Cutoff frequency, filter option #1, 4-pole [2] [4] — 1000 — Hz tSigDelay Signal delay (sinc filter to output delay, excluding the PABS LPF) [4] — — 128 μs Tr_800Hz_LPF — — 0.53 ms Tr_1kHz_LPF Response time 10 % to 90 % of the final output value to input pressure step pulse. [4] — — 0.42 ms TTD_800Hz_LPF — — 1.2 ms TTD_1kHz_LPF Total delay time Total delay (settling time) of the final output value to input pressure step pulse. [4] — — 1.0 ms tST_INIT PABS startup common mode verification test time [4] — — 24 ms tST_CMCONT PABS continuous common mode verification response time PABS error equivalent to 50 kPa [4] — — 4 s tST_Resp_1000_4 Self-test response time: self-test activation/deactivation to final value LPF = 1000 Hz, 4-pole [4] — — 2.016 ms Table 105. Dynamic characteristics...continued FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.2 — 28 June 2023 56 / 72 |
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