FXPS7115D4S datasheet(38/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

2. Add a delay of minimum 50 µs.

3. Optional: Execute a register read of the UF_REGION_R register and confirm the REGION_ACTIVE[3:0] bits

match the values written to the REGION_LOAD[3:0] bits in the UF_REGION_W register.

REGION_ACTIVE[3:0]

OTP register addresses loaded into the readable registers

Load of OTP registers is in process

The contents of the shared registers has been over-written by the user

0010 through 1001

not applicable

Address Range A0h through AFh

Address Range B0h through BFh

Address Range C0h through CFh

Address Range D0h through DFh

Address Range E0h through EFh

Address Range F0h through FFh

Table 54. REGION_ACTIVE Bit Definitions

4. Execute a Register Read of the desired registers from the UF0, UF1 or F register section. Complete all

desired Register Reads of the selected UF Region.

5. Repeat steps 1 through 4 for the next desired UF region to read.

Notes:

• The user must take care to ensure that the desired registers are addressed. For example, if the

REGION_LOAD bits are set to Ah and the user executes a read of address C2h, the contents of registers A2h

is transmitted. No error detection is included other than a read of the REGION_ACTIVE bits.

• In SPI and I2C modes, once the ENDINIT bit is set, writes to registers other than the RESET[1:0] bits are

inhibited. For this reason, reads of the UF0, UF1, and F registers are only possible for the region selected by

the REGION_ACTIVE bits at the time ENDINIT is set.

7.7.7 SOURCEID_x - source identification registers (address 1Ah, 1Bh)

The source identification registers are user programmed read/write registers that contain the source

identification information used in SPI Mode. These registers are included in the read/write array error detection.

Bit

Symbol

SID0_EN

reserved

SOURCEID_0[3:0]

Factory default

Access

R/W

Table 55. SOURCEID_0 - source identification register (address 1Ah) bit allocation

Bit

Symbol

SID1_EN

reserved

SOURCEID_1[3:0]

Factory default

Access

R/W

Table 56. SOURCEID_1 - source identification register (address 1Bh) bit allocation

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1.2 — 28 June 2023

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