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FXPS7115D4S датащи(PDF) 31 Page - NXP Semiconductors |
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FXPS7115D4S датащи(HTML) 31 Page - NXP Semiconductors |
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31 / 72 page ![]() NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa 7.7 Register information 7.7.1 COUNT - rolling counter register (address 00h) The count register is a read-only register that provides the current value of a free-running 8-bit counter derived from the primary oscillator. A 10-bit prescaler divides the primary oscillator frequency by 1000. Therefore, the value in the register increases by one count every 100 μs and the counter rolls over every 25.6 ms. Bit 7 6 5 4 3 2 1 0 Symbol COUNT[7:0] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Table 36. COUNT - rolling counter register (address 00h) bit allocation 7.7.2 Device status registers The device status registers are read-only registers that contain device status information. These registers are readable in SPI or I2C mode. 7.7.2.1 DEVSTAT - device status register (address 01h) Bit 7 6 5 4 3 2 1 0 Symbol DSP_ERR reserved COMM_ ERR MEMTEMP_ ERR SUPPLY_ ERR TES TMODE DEVRES DEVINIT Reset 1 reserved 0 0 x 0 1 1 Access R R R R R R R R Table 37. DEVSTAT - device status register (address 01h) bit allocation Bit Symbol Description 7 DSP_ERR The DSP error flag is set if a DSP-specific error is present in the pressure signal DSP: DSP_ERR = DSP_STAT[ST_INCMPLT] | DSP_STAT[CM_ERROR] | DSP_STAT[ST_ ERROR] 5 COMM_ERR The communication error flag is set if any bit in DEVSTAT3 is set: COMM_ERR = MISO_ERR 4 MEMTEMP_ERR The memory error flag is set if any bit in DEVSTAT2 is set: MEMTEMP_ERR = F_OTP_ERR | U_OTP_ERR | U_RW_ERR | U_W_ACTIVE | TEMP0_ERR 3[1] SUPPLY_ERR The supply error flag is set if any bit in DEVSTAT1 is set: SUPPLY_ERR = VCCUV_ERR | INTREG_ERR | INTREGA_ERR | INTREGF_ERR | CONT_ERR 2 TESTMODE The test mode bit is set if the device is in test mode. The TESTMODE bit can be cleared by a test mode operation or by a power cycle. 0 — Test mode is not active 1 — Test mode is active Table 38. DEVSTAT - device status register (address 01h) bit description FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Objective data sheet Rev. 1.2 — 28 June 2023 31 / 72 |
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