FXPS7115D4S datasheet(52/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.32 Invalid register addresses

A register read command to a register address outside the addresses listed in Section 7.6 "User-accessible

data array" results in a valid response. The data for the registers are '00h'.

A register write command to a register address outside the addresses listed in Section 7.6 "User-accessible

data array" is not executable, but results in a valid response. The data for the registers are '00h'.

A register write command to a read-only register is not executable, but results in a valid response. The data for

the registers is the current content of the registers.

7.8 Read/write register array CRC verification

The writable registers (all registers except for the DEVLOCK_WR register) are verified by a continuous 4-

bit CRC that is calculated on the entire array once ENDINIT is set. The CRC verification uses a generator

polynomial of g(x) = X4 + X3 + 1, with a seed value = '0000'.

8 Maximum ratings

Absolute maximum ratings are the limits that the device can be exposed to without permanently damaging

it. Absolute maximum ratings are stress ratings only; functional operation at these ratings is not guaranteed.

Exposure to absolute maximum ratings conditions for extended periods might affect device reliability.

This device contains circuitry to protect against damage due to high static voltage or electrical fields. NXP

advises that normal precautions be taken to avoid application of any voltages higher than maximum-rated

voltages to this high-impedance circuit.

Symbol

Parameter

Conditions

Min

Max

Unit

VCCMAX

Supply Voltage

VCC, VCCIO

[1] —

+6.0

hDROP

Drop shock

To concrete, tile or steel surface, 10 drops,

any orientation

[2] —

1.2

Tstg

Storage

[2] –40

+130

°C

Temperature range

Junction

[2] [3] –40

+150

°C

PMAX

Continuous (tested at 10 s)

[1] —

150

kPa

PBURST

Maximum absolute pressure

Burst (tested at 100 ms)

[1] —

345

kPa

PMIN

Minimum absolute pressure

Continuous

[1] —

kPa

fSEAL

Pressure sealing force

Applied to top face of package

[1] —

θJA

Thermal resistance

[4] —

120

°C/W

ESD and latch-up protection characteristics

VESD

Human body model (HBM)

[2] –2000

2000

VESD

Electrostatic discharge (per

AEC-Q100, Rev H)

Charge device model (CDM)

[2] [5] –500

500

Table 102. Maximum ratings

[1]

Parameter verified by parametric and functional validation.

[2]

Parameter verified by qualification testing (Per AEC-Q100 Rev H or per NXP specification).

[3]

Functionality verified by modeling, simulation and/or design verification.

[4]

Thermal resistance provided with device mounted to a two-layer, 1.6 mm FR-4 PCB as documented in AN1902[1] with one signal layer and one ground

layer.

[5]

CDM tested at ±750 V for corner pins and ±500 V for all other pins.

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1.2 — 28 June 2023

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