VL6524 datasheet(34/70 Pages) STMICROELECTRONICS

34 / 70 page

Host communication - I²C control interface

VL6524/VS6524

34/70

Figure 20.

Device addresses

R/W = 0 then the master (transmitter) is writing to the slave (receiver).

R/W = 1 the master (receiver) is reading from the slave (transmitter).

The addressed slave acknowledges the device address.

Data transmitted on the bus

When a write is performed then master outputs 8-bits of data on SDA (MS Bit

first).

When a read is performed then slave outputs 8-bits of data on SDA (MS Bit First).

Data receive acknowledge

When a write is performed slave acknowledges data.

When a read is performed master acknowledges data.

●

Repeat 4 and 5 until all the required data has been written or read.

●

Minimum number of data bytes for a read =1 (Shortest Message length is 2-bytes).

●

The master outputs a negative acknowledge for the data when reading the last byte of

data. This causes the slave to stop the output of data and allows the master to generate

a STOP condition.

Master generates a STOP condition or a repeated START.

Data valid

The data on SDA is stable during the high period of SCL. The state of SDA is changed

during the low phase of SCL. The only exceptions to this are the start (S) and stop (P)

conditions as defined below. (See

Figure 33: Timing specification and Table 38: Timing

specification).

Figure 21.

SDA data valid

R/W

Sensor Address

Sensor write Address 20H

Sensor read Address 21H

Data line

stable

Data valid

Data line

stable

Data valid

Data change

SDA

SCL

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