VL6524 datasheet(61/70 Pages) STMICROELECTRONICS

номер детали	VL6524

подробное описание детали	VGA single-chip camera module

PDF	70 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

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VL6524/VS6524

Electrical characteristics

61/70

Figure 32.

Voltage level specification

Table 38.

Timing specification(1)

All values are referred to a VIHmin = 0.9 VDD and VILmax = 0.1 VDD

Symbol

Parameter

Standard mode

Fast mode

Unit

Min.

Max.

Min.

Max.

fSCL

SCL clock frequency

100

400

kHz

tHD;STA

Hold time for a repeated

start

4.0

0.6

µs

tLOW

LOW period of SCL

4.7

1.3

µs

tHIGH

HIGH period of SCL

4.0

0.6

µs

tSU;STA

Set-up time for a repeated

start

4.7

0.6

µs

tHD;DAT

Data hold time (1)

300

tSU;DAT

Data Set-up time (1)

250

100

Rise time of SCL, SDA

1000

20+0.1Cb

(2)

Cb = capacitance of one bus line in pF

300

Fall time of SCL, SDA

300

20+0.1Cb

(2)

300

tSU;STO

Set-up time for a

stop

4.0

0.6

µs

tBUF

Bus free time between a

stop and

start

4.7

1.3

µs

Capacitive Load for each bus line

400

VnL

Noise Margin at the LOW level for

each connected device (including

hysteresis)

0.1 VDD

VnH

Noise Margin at the HIGH level for

each connected device (including

hysteresis)

0.2 VDD

VOH = 0.8 * VDD

VOL = 0.2 * VDD

Input voltage levels

Output voltage levels

VIH

VIL

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