VL6524 datasheet(60/70 Pages) STMICROELECTRONICS

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Electrical characteristics

VL6524/VS6524

60/70

13.4

AC electrical characteristics

13.4.1

External clock

The VL6524/VS6524 requires an external clock. This clock is a CMOS digital input. The

clock input is fail-safe in power down mode.

13.4.2

Chip enable

CE is a CMOS digital input. The module is powered down when a logic 0 is applied to CE.

See

Chapter 4 for power down and for power-up sequence.

13.4.3

I²C slave interface

VL6524/VS6524 contains an I²C-type interface using two signals: a bidirectional serial data

line (SDA) and an input-only serial clock line (SCL). See

Chapter 10 for detailed description

of protocol.

Table 36.

External clock

CLK

Range

Unit

Min.

Typ.

Max.

DC coupled square wave

VDD

Clock frequency (normal operation)

6.50

6.50, 8.40, 9.60, 9.72, 12.00,

13.00, 16.80, 19.20, 19.44

MHz

Table 37.

Serial interface voltage levels(1)

Maximum VIH = VDDmax + 0.5 V

Symbol

Parameter

Standard Mode

Fast Mode

Unit

Min.

Max.

Min.

Max.

VHYS

Hysteresis of Schmitt Trigger

Inputs

VDD > 2 V

N/A

0.05 VDD

-V

VDD < 2V

N/A

0.1 VDD

-V

LOW level output voltage

(open drain) at 3mA sink current

VOL1

VDD > 2 V

0.4

VOL3

VDD < 2V

N/A

0.2 VDD

VOH

HIGH level output voltage

N/A

0.8 VDD

tOF

Output fall time from VIHmin to

VILmax with a bus capacitance

from 10 pF to 400 pF

250

20+0.1Cb

(2)

Cb = capacitance of one bus line in pF

250

tSP

Pulse width of spikes which must

be suppressed by the input filter

N/A

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