VL6524 datasheet(29/70 Pages) STMICROELECTRONICS

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VL6524/VS6524

Data synchronization methods

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8.2

VSYNC and HSYNC

The VL6524/VS6524 can provide two programmable hardware synchronization signals:

VSYNC and HSYNC. The position of these signals within the output frame can be

programmed by the user or an automatic setting can be used where the signals track the

active video portion of the output frame regardless of its size.

8.2.1

Horizontal synchronization signal (HSYNC)

The HSYNC signal is controlled by the

bHSyncSetup register (Table 29). The following

options are available:

●

enable/disable

●

select polarity

●

all lines or active lines only

●

manual or automatic

In automatic mode the HSYNC signal envelops all the active video data on every line in the

output frame regardless of the programmed image size. Line codes (if selected) fall outside

the HSYNC envelope as shown in

Figure 15.

HSYNC timing example

If manual mode is selected then the pixel positions for HSYNC rising edge and falling edge

are programmable. The pixel position for the rising edge of HSYNC is programmed in the

bHsyncRisingH, bHsyncRisingL registers. The pixel position for the falling edge of HSYNC

is programmed in the

bHsyncFallingH and bHsyncFallingL registers (Table 29).

Frame Start

FF 00 00 02

Frame End

FF 00 00 03

Table 5.

Mode 2 - embedded synchronization code definition

Name

Description

4-byte sequence

SAV Code

EAV Code

ACTIVE VIDEO DATA

hsync=1

EAV Code

BLANKING DATA

hsync=0

00 00 XY 80 10 80 10 80 10

80 10

00 00 XY

D0 D1 D2 D3 D0 D1 D2 D3

D2 D3 FF 00 00 XY

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