MC68340 datasheet(124/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

4- 27

PIV7–PIV0—Periodic Interrupt Vector Bits 7–0

These bits contain the value of the vector generated during an IACK cycle in response

to an interrupt from the periodic timer. When the SIM40 responds to the IACK cycle, the

periodic interrupt vector from the PICR is placed on the bus. This vector number is

multiplied by four to form the vector offset, which is added to the vector base register to

obtain the address of the vector.

4.3.2.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for

prescaling the software watchdog and periodic timer as well as the count value for the

periodic timer. This register can be read or written at any time. Bits 15–10 are not

implemented and always return zero when read. A write does not affect these bits.

PITR

$024

9876543210

000000

SWP

PTP

PITR7

PITR6

PITR5

PITR4

PITR3

PITR2

PITR1

PITR0

RESET:

000000

MODCK MODCK

00000000

Supervisor Only

Bits 15–10—Reserved

SWP—Software Watchdog Prescale

This bit controls the software watchdog clock source as shown in 4.3.2.5 System

Protection Control Register (SYPCR).

1 = Software watchdog clock prescaled by a value of 512.

0 = Software watchdog clock not prescaled.

The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset.

PTP—Periodic Timer Prescaler Control

This bit contains the prescaler control for the periodic timer.

1 = Periodic timer clock prescaled by a value of 512.

0 = Periodic timer clock not prescaled.

The PTP reset value is the inverse of the MODCK bit state on the rising edge of reset.

PITR7–PITR0—Periodic Interrupt Timer Register Bits 7–0

The remaining bits of the PITR contain the count value for the periodic timer. A zero

value turns off the periodic timer.

Freescale Semiconductor, Inc.

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