MC68340 datasheet(36/441 Pages) FREESCALE

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MC68340 USER’S MANUAL

MOTOROLA

2.1 SIGNAL INDEX

The input and output signals for the MC68340 are listed in Table 2-1. The name,

mnemonic, and brief functional description are presented. For more detail on each signal,

refer to the signal paragraph. Guaranteed timing specifications for the signals listed in

Table 2-1 can be found in Section 11 Electrical Characteristics.

Table 2-1. Signal Index

Signal Name

Mnemonic

Function

Input/

Output

Address Bus

A23–A0

Lower 24 bits of the address bus

Out

Address Bus/Port A7–A0/

Interrupt Acknowledge

A31–A24

Upper eight bits of the address bus, parallel I/O port, or

interrupt acknowledge lines

Out/I/O/Out

Data Bus

D15–D0

The 16-bit data bus used to transfer byte or word data

I/O

Function Codes

FC3–FC0

Identify the processor state and the address space of the

current bus cycle

Out

Chip Select 3–1/

Interrupt Request Level/

Port B4, B2, B1

CS3–CS1

Enables peripherals at programmed addresses, interrupt

priority level to the CPU32, or parallel I/O port

Out/In/

I/O

Chip Select 0/Autovector

CS0

Enables peripherals at programmed addresses or

requests an automatic vector

Out/In

Bus Request

Indicates that an external device requires bus mastership

Bus Grant

Indicates that current bus cycle is complete and the

MC68340 has relinquished the bus

Out

Bus Grant Acknowledge

BGACK

Indicates that an external device has assumed bus

mastership

Data and Size

Acknowledge

DSACK1,

DSACK0

Provides asynchronous data transfers and dynamic bus

sizing

Read-Modify-Write Cycle

RMC

Identifies the bus cycle as part of an indivisible read -

modify-write operation

Out

Address Strobe

Indicates that a valid address is on the address bus

Out

Data Strobe

During a read cycle,

DS indicates that an external device

should place valid data on the data bus. During a write

cycle,

DS indicates that valid data is on the data bus.

Out

Size

SIZ1, SIZ0

Indicates the number of bytes remaining to be transferred

for this cycle

Out

Read/Write

Indicates the direction of data transfer on the bus

Out

Interrupt Request Level/

Port B7, B6, B5, B3

IRQ7, IRQ6,

IRQ5, IRQ3

Provides an interrupt priority level to the CPU32 or

becomes a parallel I/O port

In/I/O

Reset

RESET

System reset

I/O

Halt

HALT

Suspends external bus activity

I/O

Bus Error

BERR

Indicates an invalid bus operation is being attempted

System Clock

CLKOUT

System clock out

Out

Crystal Oscillator

EXTAL, XTAL

Connections for an external crystal or oscillator to the

internal oscillator circuit

In, Out

External Filter Capacitor

XFC

Connection pin for an external capacitor to filter the circuit

of the phase-locked loop

Freescale Semiconductor, Inc.

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