MC68340 datasheet(65/441 Pages) FREESCALE

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MC68340 USER’S MANUAL

MOTOROLA

3.3 DATA TRANSFER CYCLES

The transfer of data between the MC68340 and other devices involves the following

signals:

• Address Bus A31–A0

• Data Bus D15–D0

• Control Signals

The address bus and data bus are parallel, nonmultiplexed buses. The bus master moves

data on the bus by issuing control signals, and the bus uses a handshake protocol to

ensure correct movement of the data. In all bus cycles, the bus master is responsible for

de-skewing all signals it issues at both the start and end of the cycle. In addition, the bus

master is responsible for de-skewing the acknowledge and data signals from the slave

devices. The following paragraphs define read, write, and read-modify-write cycle

operations. Each bus cycle is defined as a succession of states that apply to the bus

operation. These states are different from the MC68340 states described for the CPU32.

The clock cycles used in the descriptions and timing diagrams of data transfer cycles are

independent of the clock frequency. Bus operations are described in terms of external bus

states.

3.3.1 Read Cycle

During a read cycle, the MC68340 receives data from a memory or peripheral device. If

the instruction specifies a long-word or word operation, the MC68340 attempts to read two

bytes at once. For a byte operation, the MC68340 reads one byte. The section of the data

bus from which each byte is read depends on the operand size, address signal A0, and

the port size. Refer to 3.2.1 Dynamic Bus Sizing and 3.2.2 Misaligned Operands for

more information. Figure 3-7 is a flowchart of a word read cycle.

BUS MASTER

SLAVE

ADDRESS DEVICE

1. SET R/W TO READ

2. DRIVE ADDRESS ON A31–A0

3. DRIVE FUNCTION CODE ON FC3–FC0

4. DRIVE SIZE PINS FOR OPERAND SIZE

ACQUIRE DATA

1. LATCH DATA

5. ASSERT AS AND DS

START NEXT CYCLE

2. NEGATE AS AND DS

1. DECODE ADDRESS

2. PLACE DATA ON D15–D0

PRESENT DATA

3. DRIVE DSACKx SIGNALS

TERMINATE CYCLE

1. REMOVE DATA FROM D15–D0

2. NEGATE DSACKx

Figure 3-7. Word Read Cycle Flowchart

Freescale Semiconductor, Inc.

For More Information On This Product,

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