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MC68340 датащи(PDF) 122 Page - Freescale Semiconductor, Inc |
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MC68340 датащи(HTML) 122 Page - Freescale Semiconductor, Inc |
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122 / 441 page ![]() MOTOROLA MC68340 USER’S MANUAL 4- 25 SWT1, SWT0—Software Watchdog Timing These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula: divide count EXTAL frequency The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the software watchdog timeout for any clock frequency. The timeout periods are listed for a 32.768-kHz crystal used with the VCO and for a 16.777-MHz external oscillator. Table 4-7. Deriving Software Watchdog Timeout SWP SWT1 SWT0 Software Timeout Period 32.768-kHz Crystal Period 16.777-MHz External Clock Period 00 0 29/EXTAL Input Frequency 15.6 ms 30 µs 00 1 211 /EXTAL Input Frequency 62.5 ms 122 µs 01 0 213 /EXTAL Input Frequency 250 ms 488 µs 01 1 215 /EXTAL Input Frequency 1 s 1.95 ms 10 0 218 /EXTAL Input Frequency 8 s 15.6 ms 10 1 220 /EXTAL Input Frequency 32 s 62.5 ms 11 0 222 /EXTAL Input Frequency 128 s 250 ms 11 1 224 /EXTAL Input Frequency 512 s 1 s NOTE: When the SWP and SWT bits are modified to select a software timeout other than the default, the software service sequence ($55 followed by $AA written to the software service register) must be performed before the new timeout period takes effect. Refer to 4.2.2.5 Software Watchdog for more information. DBFE—Double Bus Fault Monitor Enable 1 = Enable double bus fault monitor function. 0 = Disable double bus fault monitor function. For more information, see 4.2.2.3 Double Bus Fault Monitor and Section 5 CPU32. BME—Bus Monitor External Enable 1 = Enable bus monitor function for an internal-to-external bus cycle. 0 = Disable bus monitor function for an internal-to-external bus cycle. For more information see 4.2.2.2 Internal Bus Monitor. BMT1, BMT0—Bus Monitor Timing These bits select the timeout period for the bus monitor (see Table 4-8). Upon reset, the bus monitor is set to 64 system clocks. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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