MC68340 datasheet(31/441 Pages) FREESCALE

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MC68340 USER’S MANUAL

1- 7

1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340

includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1

standard for boundary scan testability, often referred to as JTAG (Joint Test Action

Group).

1.3.2 Direct Memory Access Module

The most distinguishing MC68340 characteristic is the high-speed 32-bit DMA controller,

used to quickly move large blocks of data between internal peripherals, external

peripherals, or memory without processor intervention. The DMA module consists of two,

independent, programmable channels. Each channel has separate request, acknowledge,

and done signals. Each channel can operate in a single-address or a dual-address (flyby)

mode.

In single-address mode, only one (the source or the destination) address is provided, and

a peripheral device such as a serial communications controller receives or supplies the

data. An external request must start a single-address transfer. In this mode, each channel

supports 32 bits of address and 8, 16, or 32 bits of data.

In dual-address mode, two bus transfers occur, one from a source device and the other to

a destination device. Dual-address transfers can be started by either an internal or

external request. In this mode, each channel supports 32 bits of address and 8 or 16 bits

of data (32 bits require external logic). The source and destination port size can be

selected independently; when they are different, the data will be packed or unpacked. An

8-bit disk interface can be read twice before the concatenated 16-bit result is passed into

memory.

Byte, word, and long-word counts up to 32 bits can be transferred. All addresses and

transfer counters are 32 bits. Addresses increment or remain constant, as programmed.

The DMA channels support two external request modes, burst transfer and cycle steal.

Internal requests can be programmed to occupy 25, 50, 75, or 100 percent of the data bus

bandwidth. Interrupts can be programmed to postpone DMA completion.

The DMA module can sustain a transfer rate of 12.5 Mbytes/sec in dual-address mode

and nearly 50 Mbytes/sec in single-address mode @ 25.16 MHz (8.4 and 33.3 Mbytes/sec

16.78 MHz, respectively). The DMA controller arbitrates with the CPU32 for the bus in

parallel with existing bus cycles and is fully synchronized with the CPU32, eliminating all

delays normally associated with bus arbitration by allowing DMA bus cycles to butt

seamlessly with CPU bus cycles.

1.3.3 Serial Module

Most digital systems use serial I/O to communicate with host computers, operator

terminals, or remote devices. The MC68340 contains a two-channel, full-duplex USART.

An on-chip baud rate generator provides standard baud rates up to 76.8k baud

independently to each channel's receiver and transmitter. The module is functionally

equivalent to the MC68681/MC2681 DUART.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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