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CS5308GDWR28 датащи(PDF) 20 Page - ON Semiconductor

номер детали CS5308GDWR28
подробное описание детали  Two?뭁hase PWM Controller with Integrated Gate Drivers for VRM 8.5
PDF  31 Pages
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
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CS5308GDWR28 датащи(HTML) 20 Page - ON Semiconductor

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DVCi + ESRIN NIN @ dILo dt @ tON
+ ESRIN NIN @ dILo dt @ D fSW
(17)
Before the load is applied, the voltage across the input
inductor (VLi) is very small − the input capacitors charge to
the input voltage, VIN. After the load is applied the voltage
drop across the input capacitors,
DVCi, appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
LiMIN + VLi dIIN dtMAX
+ DVCi dIIN dtMAX
(18)
dIIN/dtMAX is the maximum allowable input current slew
rate (specified as 0.1 A/
ms or 0.1 × 106 A/s for VRM 8.5).
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the −26 or −52 from Micrometals, the inductance “swing”
with DC bias must be taken into account − inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
5. MOSFET & Heatsink Selection
Power dissipation, package size, and thermal solution
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches into nearly zero
voltage. However, the body diode in the synchronous
MOSFET will suffer diode losses during the non−overlap
time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
) (ILo,MAX @ Qswitch Ig @ VIN @ fSW)
) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
(19)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
Where IRMS,CNTL is the RMS value of the trapezoidal
current in the control MOSFET:
(20)
IRMS,CNTL + D
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAX 2 ) DILo 2
(21)
ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX 2 * DILo 2
(22)
IO,MAX is the maximum converter output current.
D is the duty cycle of the converter:
D + VOUT VIN
(23)
DILo is the peak−to−peak ripple current in the output
inductor of value Lo:
DILo + (VIN * VOUT) @ D (Lo @ fSW)
(24)
RDS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Qswitch is the post gate threshold portion of the
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 16.
Qswitch + Qgs2 ) Qgd
(25)
ID
VGATE
VDRAIN
QGD
QGS2
QGS1
VGS_TH
Figure 16. MOSFET Switching Characteristics
Ig is the output current from the gate driver IC.
VIN is the input voltage to the converter.
fsw is the switching frequency of the converter.



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