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CS5308

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9. Place the output capacitors (electrolytic and

ceramic) close to the processor socket or output

connector.

10. The trace from the SWNODEs to the current sense

components will be very noisy. Route this away

from more sensitive, low−level traces. The Ground

layer can be used to help isolate this trace.

11. The Gate traces are very noisy. Route these away

from more sensitive, low−level traces. Keep each

Gate signal on one layer and insure that there is an

uninterrupted return path directly below the Gate

trace. The Ground layer can be used to help isolate

these traces.

12. Don’t “daisy chain” connections to Ground from

one via. Allow each connection to Ground to have

its own via as close to the component as possible.

13. Use a slot in the ground plane from the bulk output

capacitors back to the input power connector to

prevent high currents from flowing beneath the

control IC. This slot should extend length−wise

under the control IC and separate the connections

to “signal ground” and “power ground.” Examples

of signal ground include the capacitors at COMP,

CSREF, REF, and VTTCT, the resistors at ROSC and

ILIM, and the LGND pin to the controller. Examples

of power ground include the capacitors to VCCH1,

VCCH2 and VCCL12, the Source of the synchronous

MOSFETs, and the PGND pin to the controller.

14. The CSREF sense point should be equidistant

between the output inductors to equalize the PCB

resistance added to the current sense paths. This

will insure acceptable current sharing. Also, route

the CSREF connection away from noisy traces such

as the SWNODEs and GATE traces. If noise from

the SWNODEs or GATE signals capacitively

couples to the CSREF trace the external ramps will

be very noise and voltage jitter will result.

15. Ideally, the SWNODEs are exactly the same shape

and the current sense points (connections to RCS1

and RCS2) are made at identical locations to equalize

the PCB resistance added to the current sense paths.

This will help to insure acceptable current sharing.

16. Place the 0.1

mF ceramic capacitors, CQ1 and CQ2,

close to the drains of the MOSFETs Q1 and Q2,

respectively.

Design Procedure

1. Output Capacitor Selection

The output capacitors filter the current from the output

inductor and provide a low impedance for transient load

current changes. Typically, microprocessor applications

will require both bulk (electrolytic, tantalum) and low

impedance, high frequency (ceramic) types of capacitors.

The bulk capacitors provide “hold up” during transient

loading. The low impedance capacitors reduce steady−state

ripple and bypass the bulk capacitance when the output

current changes very quickly. The microprocessor

manufacturers usually specify a minimum number of

ceramic capacitors. The designer must determine the

number of bulk capacitors.

Choose the number of bulk output capacitors to meet the

peak transient requirements. The formula below can be used

to provide a starting point for the minimum number of bulk

capacitors (NOUT,MIN):

NOUT,MIN + ESR per capacitor @

DIO,MAX

DVO,MAX

(1)

In reality, both the ESR and ESL of the bulk capacitors

determine the voltage change during a load transient

according to:

DVO,MAX + (DIO,MAX Dt) @ ESL ) DIO,MAX @ ESR (2)

Unfortunately, capacitor manufacturers do not specify the

ESL of their components and the inductance added by the

PCB traces is highly dependent on the layout and routing.

Therefore, it is necessary to start a design with slightly more

than the minimum number of bulk capacitors and perform

transient testing or careful modeling/simulation to

determine the final number of bulk capacitors.

2. Output Inductor Selection

The output inductor may be the most critical component

in the converter because it will directly effect the choice of

other components and dictate both the steady−state and

transient performance of the converter. When selecting an

inductor the designer must consider factors such as DC

current, peak current, output voltage ripple, core material,

magnetic saturation, temperature, physical size, and cost

(usually the primary concern).

In general, the output inductance value should be as low

and physically small as possible to provide the best transient

response and minimum cost. If a large inductance value is

used, the converter will not respond quickly to rapid changes

in the load current. On the other hand, too low an inductance

value will result in very large ripple currents in the power

components (MOSFETs, capacitors, etc.) resulting in

increased dissipation and lower converter efficiency. Also,

increased ripple currents will force the designer to use

higher rated MOSFETs, oversize the thermal solution, and

use more, higher rated input and output capacitors − the

converter cost will be adversely effected.

One method of calculating an output inductor value is to

size the inductor to produce a specified maximum ripple

current in the inductor. Lower ripple currents will result in

less core and MOSFET losses and higher converter

efficiency. Equation 3 may be used to calculate the

minimum inductor value to produce a given maximum

ripple current (

a) per phase. The inductor value calculated

by this equation is a minimum because values less than this

will produce more ripple current than desired. Conversely,

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