CS5308GDWR28 datasheet(15/31 Pages) ONSEMI

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CS5308

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current applications a droop resistor can provide fast

accurate adaptive positioning. However, at high currents the

loss in a droop resistor becomes excessive. For example; in

a 50 A converter a 1 m

W resistor to provide a 50 mV change

in output voltage between no load and full load would

dissipate 2.5 Watts.

Lossless adaptive positioning is an alternative to using a

droop resistor, but must respond to changes in load current.

Figure 13 shows how adaptive positioning works. The

waveform labeled normal shows a converter without

adaptive positioning. On the left, the output voltage sags

when the output current is stepped up and later overshoots

when current is stepped back down. With fast (ideal)

adaptive positioning the peak to peak excursions are cut in

half. In the slow adaptive positioning waveform the output

voltage is not repositioned quickly enough after current is

stepped up and the upper limit is exceeded.

Adaptive Positioning

Normal

Fast

Slow

Limits

Figure 13. Adaptive Positioning

The controller can be configured to adjust the output

voltage based on the output current of the converter. (Refer

to the application diagram in Figure 1.) To set the no−load

positioning, a resistor is placed between the output voltage

and VFB pin. The VFB bias current will develop a voltage

across the resistor to adjust the no−load output voltage. The

VFB bias current is dependent on the value of ROSC as shown

in the data sheets.

During no−load conditions the VDRP pin is at the same

voltage as the VFB pin, so none of the VFB bias current flows

through the VDRP resistor. When output current increases

the VDRP pin increases proportionally and the VDRP pin

current offsets the VFB bias current and causes the output

voltage to decrease.

The response during the first few microseconds of a load

transient are controlled primarily by power stage output

impedance and the ESR and ESL of the output filter. The

transition between fast and slow positioning is controlled

by the total ramp size and the error amp compensation. If

the current signal is too large or the error amp too slow there

will be a long transition to the final voltage after a transient.

This will be most apparent with lower capacitance output

filters.

Error Amp Compensation & Tuning

The transconductance error amplifier requires a capacitor

(CCMP2 in the Applications Diagram) between the COMP

pin and GND for two reasons. First, this capacitor stabilizes

the transconductance error amplifier. Values less than a few

nF may cause oscillations of the COMP voltage. These

oscillations will increase the output voltage jitter. Second,

this capacitor sets the Soft Start time when power is applied

to the converter or the converter is enabled. The internal

error amplifier will source approximately 30

mA during Soft

Start and no switching will occur until the COMP voltage

exceeds the Channel Startup Offset (nominally 0.4 V). The

COMP voltage will ramp up to the value shown previously

(repeated here for convenience):

VCOMP + VOUT @0 A ) Channel_Startup_Offset

) Int_Ramp ) GCSA @ Ext_Ramp 2

The RC network between the COMP pin and the Soft Start

capacitor (RCMP1 and CCMP1) allows the COMP voltage to

slew quickly during transient loading of the converter.

Without this network the error amplifier would have to drive

the large Soft Start/Stability capacitor directly, which would

drastically limit the slew rate of the COMP voltage. The

RCMP1/CCMP1 network allows the COMP voltage to undergo

a step change in voltage of approximately RCMP1 • ICOMP.

The capacitor (CAMP) between the COMP pin and the

inverting error amplifier input (the VFB pin) and the parallel

combination of the resistors RFBK1 and RDRP1 determine the

bandwidth of the error amplifier. The gain of the error

amplifier crosses 0 dB at a high enough frequency to give a

quick transient response, but well below the switching

frequency to minimize ripple and noise on the COMP pin.

A capacitor in parallel with the VFB resistor (CFBK2) adds a

zero to boost phase near the crossover frequency to improve

loop stability.

Setting−up and tuning the error amplifier is a three step

process. First, the no−load and full−load adaptive voltage

positioning (AVP) are set using RFBK1 and RDRP1,

respectively. Second, the current sense time constant and

error amplifier gain are adjusted with RCSn and CAMP while

monitoring VOUT during transient loading. Lastly, the

peak−to−peak voltage ripple on the COMP pin is examined

when the converter is fully loaded to insure low output

voltage jitter. The details of this process are covered in the

Design Procedure section.

Undervoltage Lockout (UVLO)

The controller has undervoltage lockout functions

connected to two pins. One, intended for the logic and

low−side drivers, with approximately a 4.2 V turn−on

threshold is connected to the VCC pin. A second, for the high

side drivers, with approximately an 8.25 V threshold, is

connected to the VCCH pin.

The UVLO threshold for the high side drivers varies with

the part type. In many applications this function will be

disabled or will only check that the applicable supply is on

− not that is at a high enough voltage to run the converter. See

individual data sheets for more information on UVLO.

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