CS5308GDWR28 datasheet(19/31 Pages) ONSEMI

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CS5308

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For a two−phase converter with perfect efficiency (

h = 1),

the worst case input ripple−current will occur when the

converter is operating at a 25% duty cycle. At this operating

point, the parallel combination of input capacitors must

support an RMS ripple current equal to 25% of the

converter’s DC output current. At other duty cycles, the

ripple−current will be less. For example, at a duty cycle of

either 10% or 40%, the two−phase input ripple−current will

be approximately 20% of the converter’s DC output current.

In general, capacitor manufacturers require derating to the

specified ripple−current based on the ambient temperature.

More capacitors will be required because of the current

derating. The designer should be cognizant of the ESR of the

input capacitors. The input capacitor power loss can be

calculated from:

PCIN + ICIN,RMS2 @ ESR_per_capacitor NIN (13)

Low ESR capacitors are recommended to minimize losses

and reduce capacitor heating. The life of an electrolytic

capacitor is reduced 50% for every 10°C rise in the

capacitor’s temperature.

4. Input Inductor Selection

The use of an inductor between the input capacitors and

the power source will accomplish two objectives. First, it

will isolate the voltage source and the system from the noise

generated in the switching supply. Second, it will limit the

inrush current into the input capacitors at power up. Large

inrush currents will reduce the expected life of the input

capacitors. The inductor’s limiting effect on the input

current slew rate becomes increasingly beneficial during

load transients.

5.0 V

TBD

2 × 6SP680

ESRCi

13 m/2 = 6.5 m

825 nH

ESRCo

23 m/5 = 4.6 m

14 u(t)

5 × 6.3ZA1000M10x16

Vi(t = 0) = 5.0 V

SWNODE

Vo(t = 0) = 1.745 V

VCi

ILo

VOUT

ILi

MAX dI/dt occurs in

first few PWM cycles.

Figure 15. Calculating the Input Inductance

−

The worst case input current slew rate will occur during

the first few PWM cycles immediately after a step−load

change is applied as shown in Figure 15. When the load is

applied, the output voltage is pulled down very quickly.

Current through the output inductors will not change

instantaneously so the initial transient load current must be

conducted by the output capacitors. The output voltage will

step downward depending on the magnitude of the output

current (IO,MAX), the per capacitor ESR of the output

capacitors (ESROUT), and the number of the output

capacitors (NOUT) as shown in Figure . Assuming the load

current is shared equally between the two phases, the output

voltage at full, transient load will be:

VOUT,FULL−LOAD +

(14)

VOUT,NO−LOAD * (IO,MAX 2) @ ESROUT NOUT

When the control MOSFET (Q1 in Figure 15) turns ON,

the input voltage will be applied to the opposite terminal of

the output inductor (the SWNODE). At that instant, the

voltage across the output inductor can be calculated as:

DVLo + VIN * VOUT,FULL−LOAD

(15)

+ VIN * VOUT,NO−LOAD

) (IO,MAX 2) @ ESROUT NOUT

The differential voltage across the output inductor will

cause its current to increase linearly with time. The slew rate

of this current can be calculated from:

dILo dt + DVLo Lo

(16)

Current changes slowly in the input inductor so the input

capacitors must initially deliver the vast majority of the

input current. The amount of voltage drop across the input

capacitors (

DVCi) is determined by the number of input

capacitors (NIN), their per capacitor ESR (ESRIN), and the

current in the output inductor according to:

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