CS5308GDWR28 datasheet(12/31 Pages) ONSEMI

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CS5308

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Figure 9. Enhanced V2 Control Employing Resistive Current Sensing and Additional Internal Ramp

SWNODE

RLn

RSn

CSn

CSA

COn

CSREF

VOUT

(VCORE)

“Fast−Feedback”

Connection

PWM

COMP

To F/F

Reset

Channel

Start−Up

Offset

E.A.

DAC

Out

VFB

COMP

Internal Ramp

n = 1 or 2

− +

Enhanced V2 responds to disturbances in VCORE by

employing both “slow” and “fast” voltage regulation. The

internal error amplifier performs the slow regulation.

Depending on the gain and frequency compensation set by

the amplifier’s external components, the error amplifier will

typically begin to ramp its output to react to changes in the

output voltage in 1−2 PWM cycles. Fast voltage feedback is

implemented by a direct connection from VCORE to the

non−inverting pin of the PWM comparator via the

summation with the inductor current, internal ramp, and

OFFSET. A rapid increase in load current will produce a

negative offset at VCORE and at the output of the summer.

This will cause the PWM duty cycle to increase almost

instantly. Fast feedback will typically adjust the PWM

duty−cycle in one PWM cycle.

As shown in Figure 9, a “partial” internal ramp (nominally

125 mV at a 50% duty cycle) is added to the inductor current

ramp at the positive terminal of the PWM comparator. This

additional ramp compensates for propagation time delays

from the current sense amplifier (CSA), the PWM

comparator, and the MOSFET gate drivers. As a result, the

minimum ON time of the controller is reduced and lower

duty cycles may be achieved at higher frequencies. Also, the

additional ramp reduces the reliance on the inductor current

ramp and allows greater flexibility when choosing the

output inductor and the RCSnCCSn (n = 1 or 2) time constant

of the feedback components from VCORE to the CSn pin.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. When the average output

current is zero, the COMP pin will be:

VCOMP + VOUT @0 A ) Channel_Startup_Offset

) Int_Ramp ) GCSA @ Ext_Ramp 2

Int_Ramp is the “partial” internal ramp value at the

corresponding duty cycle, Ext_Ramp is the peak−to−peak

external steady−state ramp at 0 A, GCSA is the Current Sense

Amplifier Gain (nominally 3.5 V/V), and the Channel

Startup Offset is typically 0.40 V. The magnitude of the

Ext_Ramp can be calculated from:

Ext_Ramp + D @ (VIN * VOUT) (RCSn @ CCSn @ fSW)

For example, if VOUT at 0 A is set to 1.745 V with AVP and

the input voltage is 5.0 V, the duty cycle (D) will be 1.745/5.0

or 35%. Int_Ramp will be 125 mV • 35/50 = 87.5 mV.

Realistic values for RCSn, CCSn and fSW are 60 kW, 0.01 mF,

and 300 kHz

- using these Ext_Ramp will be 6.3 mV.

VCOMP + 1.745 V ) 0.40 V ) 87.5 mV

) 3.5 V V @ 6.3 mV 2

+ 2.244 Vdc.

If the COMP pin is held steady and the inductor current

changes, there must also be a change in the output voltage.

Or, in a closed loop configuration when the output current

changes, the COMP pin must move to keep the same output

voltage. The required change in the output voltage or COMP

pin depends on the scaling of the current feedback signal and

is calculated as:

DV + RS @ GCSA @ DIOUT.

The single−phase power stage output impedance is:

Single Stage Impedance + DVOUT DIOUT+RS @ GCSA

The multi−phase power stage output impedance is the

single−phase output impedance divided by the number of

phases. The output impedance of the power stage determines

how the converter will respond during the first few

microseconds of a transient before the feedback loop has

repositioned the COMP pin.

The peak output current can be calculated from:

IOUT,PEAK + (VCOMP * VOUT * Offset) (RS @ GCSA)

Figure 10 shows the step response of the COMP pin at a

fixed level. Before T1 the converter is in normal steady state

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