28

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

5610 drw24

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

30 pF

1.1K

Ω

5.0 V

680

Ω

PROPAGATION DELAY

LOAD CIRCUIT

3 V

GND

Timing

Input

Data,

Enable

Input

GND

3 V

1.5 V

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

3 V

GND

GND

3 V

1.5 V

1.5 V

1.5 V

1.5 V

tW

Output

Enable

Low-Level

Output

High-Level

Output

3 V

OL

GND

≈ 3 V

1.5 V

1.5 V

1.5 V

1.5 V

OH

≈ OV

GND

OH

OL

1.5 V

1.5 V

1.5 V

1.5 V

Input

In-Phase

Output

High-Level

Input

Low-Level

Input

V

V

V

V

1.5 V

3 V

tS

th

tPLZ

tPHZ

tPZL

tPZH

tPD

tPD

(1)

Figure 21. Block Diagram of 512 x 36, 1,024 x 36 Synchronous FIFO Memory with

Programmable Flags used in Depth Expansion Configuration

NOTES:

1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)

2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.

3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the

sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.

4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:

(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.

DATA IN (Dn)

READ CLOCK (CLKB)

READ ENABLE (ENB)

EMPTY FLAG/

OUTPUT READY (

EF/OR)

CHIP SELECT (

CSB)

DATA OUT (Qn)

TRANSFER CLOCK

5610 drw23

IDT

723663

723673

VCC

IDT

723663

723673

WRITE

READ

A0-A35

MBA

CHIP SELECT (

CSA)

WRITE SELECT (W/

RA)

WRITE ENABLE (ENA)

ALMOST-FULL FLAG (

AF)

FULL FLAG/

INPUT READY (

FF/IR)

WRITE CLOCK (CLKA)

CLKB

EF/OR

ENB

CSB

B0-B35

W/RB

MBB

CLKA

ENA

FF/IR

CSA

MBA

A0-A35

W/

RA

READ SELECT

(

W/RB)

ALMOST-EMPTY FLAG (

AE)

B0-B35

MBB

VCC

n

n

n

Qn

Dn

VCC

VCC

NOTE:

1. Includes probe and jig capacitance.

Figure 22. Load Circuit and Voltage Waveforms.