5

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

Symbol

Name

I/O

Description

PIN DESCRIPTIONS (CONTINUED)

MBF1

Mail1RegisterFlag

O

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.

Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-

HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH

following either a Reset (RS1) or Partial Reset (PRS).

MBF2

Mail2RegisterFlag

O

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.

Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-

HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH

following either a Reset (RS2) or Partial Reset (PRS).

RS1, RS2

Resets

I

A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and

setsthePortBoutputregistertoallzeroes.ALOW-to-HIGHtransitiononRS1selectstheprogramming

method (serial or parallel) and one of five programmable flag default offsets. It also configures Port

B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-

HIGH transitions of CLKB must occur while RS1 is LOW.

PRS/

PartialReset/

I

ThispinmuxedforbothPartialResetandRetransmitoperations,itisusedinconjunctionwiththeRTM

RT

Retransmit

pin.IfRTMisLOW,thenaLOWonthispininitializestheFIFOreadandwritepointerstothefirstlocation

of memory and sets the Port B output register to all zeroes. During Partial Reset, thecurrently

selectedbussize,endianarrangement,programmingmethod(serialorparallel),andprogrammable

flagsettingsareallretained.IfRTMisHIGH,thenaLOWonthispinperformsaRetransmitandinitializes

thereadpointeronly,tothefirstmemorylocation.

RTM

RetransmitMode

I

This pin is used in conjunction with the RT pin. When RTM is HIGH a Retransmit is performed when

RT is taken HIGH.

SIZE(1)

BusSizeSelect

I

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin

(Port B)

when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size

and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

W/RA

PortAWrite/

I

A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH

ReadSelect

transition of CLKA. The A0-A35 outputs are in the HIGH impedancestatewhenW/RAisHIGH.

W/RB

PortBWrite/

I

A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH

ReadSelect

transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.

NOTE:

1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or VCC.