IDT723663 datasheet(3/30 Pages) RENESAS

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IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

Communication between each port may bypass the FIFO via two mailbox

registers.Themailboxregisters'widthmatchestheselectedPortBbuswidth.

Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail

has been stored.

Two kinds of reset are available on these FIFOs: Reset and Partial Reset.

Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray

andselectsserialflagprogramming,parallelflagprogramming,oroneoffive

possibledefaultflagoffsetsettings,8,16,64,256or1,024.

PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe

memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,

programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset

is useful since it permits flushing of the FIFO memory without changing any

configurationsettings.

TheFIFOhasRetransmitcapability,aRetransmitisperformedafterfourclock

cycles of CLKA and CLKB, by taking the Retransmit pin, RT LOW while the

RetransmitModepin,RTMisHIGH.WhenaRetransmitisperformedtheread

pointerisresettothefirstmemorylocation.

Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,the

firstwordwrittentoanemptyFIFOisdepositedintothememoryarray.Aread

operation is required to access that word (along with all other words residing

inmemory).IntheFirstWordFallThroughmode(FWFT),thefirstwordwritten

to an empty FIFO appears automatically on the outputs, no read operation

required (Nevertheless, accessing subsequent words does necessitate a

formalreadrequest).ThestateoftheBE/FWFTpinduringResetdetermines

the mode in use.

The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a

combinedFull/InputReadyFlag(FF/IR).TheEFandFFfunctionsareselected

in the IDT Standard mode. EF indicates whether or not the FIFO memory is

empty. FF shows whether the memory is full or not. The IR and OR functions

areselectedintheFirstWordFallThroughmode.IRindicateswhetherornot

theFIFOhasavailablememorylocations.ORshowswhethertheFIFOhasdata

availableforreadingornot.Itmarksthepresenceofvaliddataontheoutputs.

TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogrammable

Almost-Fullflag(AF). AEindicateswhenaselectednumberofwordsremain

intheFIFOmemory.AFindicateswhentheFIFOcontainsmorethanaselected

number of words.

FF/IR andAF aretwo-stagesynchronizedtotheportclockthatwritesdata

intoitsarray.EF/ORandAEaretwo-stagesynchronizedtotheportclockthat

reads data from its array. Programmable offsets for AE and AF are loaded in

parallelusingPortAorinserialviatheSDinput.Fivedefaultoffsetsettingsare

alsoprovided.TheAEthresholdcanbesetat8,16,64,256or1,024locations

from the empty boundary and the AF threshold can be set at 8, 16, 64, 256 or

1,024locationsfromthefullboundary.AllthesechoicesaremadeusingtheFS0,

FS1 and FS2 inputs during Reset.

InterspersedParityisavailableandcanbeselectedduringaMasterReset

oftheFIFO.IfInterspersedParityisselectedthenduringparallelprogramming

oftheflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed

Parity is selected then data line A8 will become a valid bit.

Two or more devices may be used in parallel to create wider data paths. In

First Word Fall Through mode, more than one device may be connected in

seriestocreategreaterworddepths.Theadditionofexternalcomponentsis

unnecessary.

If, at any time, the FIFO is not actively performing a function, the chip will

automatically power down. During the power down state, supply current

consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol

inputs)willimmediatelytakethedeviceoutofthePowerDownstate.

TheIDT723663/723673arecharacterizedforoperationfrom0

°Cto70°C.

Industrial temperature range (-40

°C to +85°C) is available by special order.

They are fabricated using high speed, submicron CMOS technology.

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