25

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

Figure 17. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)

NOTE:

1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-

B35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8

(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and

rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.

2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 4,096 for the IDT723663, 8,192 for the IDT723673.

4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.

Figure 16. Timing for AF when the FIFO is Almost-Full (IDT Standard and FWFT Modes).

AF

CLKA

ENB

5610 drw18

ENA

CLKB

12

tSKEW2

tENS2

tENH

tPAF

tENS2

tENH

tPAF

[D-(Y+1)] Words in FIFO

(D-Y) Words in FIFO

(1)

5610 drw19

CLKA

ENA

A0-A35

MBA

CSA

W/

RA

CLKB

MBF1

CSB

MBB

ENB

B0-B35

W/RB

tENS1

tENH

tDS

tDH

tPMF

tPMF

tENS2

tENH

tDIS

tEN

tMDV

tPMR

FIFO Output Register

W1 (Remains valid in Mail1 Register after read)

tENS1

tENH

tENH

tENS2

tENH

tENS2

W1