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COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

(IDT Standard and FWFT Modes)

NOTE:

1. CSA = LOW, W/RA = HIGH, MBA = LOW.

Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

(IDT Standard and FWFT Modes)

NOTES:

1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.

2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).

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CLKA

RS1

FF/IR

A0-A35

FS1,FS0

ENA

tFSH

tWFF

tENH

tENS2

tDS

tDH

4

0,0

AF Offset

(Y)

AE Offset

(X)

First Word to FIFO1

tFSH

tFSS

FS2

tFSS

1

2

CLKA

FF/IR

tSENS

tSENH

FS0/SD(2)

tSPH

tSENS

tSENH

tFSS

tWFF

FS1/

SEN

AE Offset

(X) LSB

tSDS

tSDH

tSDS

tSDH

AF Offset

(Y) MSB

RS1

4

tFSS

tFSH

FS2

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