JS28F320J3F75 datasheet(45/67 Pages) NUMONYX

45 / 67 page

Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Datasheet

Flowchart” on page 56. Any attempt to address Program OTP Register command

outside the defined PR address space will result in a Status Register error (SR.4 will be

set). Attempting to program a locked PR segment will result in a Status Register error

(SR.4 and SR.1 will be set).

9.8.7

Locking the 128-bit OTP Protection Register

The user-programmable segment of the PR is lockable by programming Bit 1 of the

Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the

Numonyx factory to protect the unique device number. Bit 1 is set using the Protection

Program command to program “0xFFFD” to the PLR. After these bits have been

programmed, no further changes can be made to the values stored in the Protection

Note:

A0 is not used in x16 mode when accessing the protection register map. See

Table 31 for x16 addressing. In x8 mode

A0 is used, see

Table 32 for x8 addressing.

Table 29: Programming the 128-bit Protection Register Command Bus-Cycles

Command

First Bus Cycle

Second Bus Cycle

Address Bus

Data Bus

Address Bus

Data Bus

Program OTP Register

Device Address

00C0h

Table 30: Programming Protection Lock Register Command Bus-Cycles

Command

First Bus Cycle

Second Bus Cycle

Address Bus

Data Bus

Address Bus

Data Bus

Program OTP Register

Device Address

00C0h

80h

FFFDh

Figure 15: 128-bit Protection Register Memory Map

0x88

0x85

64- bit Segment

( User- Programmable)

0x84

0x81

0x80

Protection Lock Register

64- bit Segment

(Factory- Programmed)

15 14 13 12 11 10

128-Bit Protection Register

0x82

0x83

0x86

0x87

Word Address

128-Mbit: A[23:1]

64-Mbit: A[22:1]

32-Mbit: A[21:1]

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