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JS28F320J3F75 датащи(PDF) 30 Page - Numonyx B.V

номер детали JS28F320J3F75
подробное описание детали  Numonyx® Embedded Flash Memory (J3 65nm) Single Bit per Cell (SBC)
PDF  67 Pages
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производитель  NUMONYX [Numonyx B.V]
домашняя страница  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS28F320J3F75 датащи(HTML) 30 Page - Numonyx B.V

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Datasheet
29
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.4
AC Test Conditions
Note:
AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Note:
CL Includes Jig Capacitance
Table 14: Reset Specifications
#
Symbol
Parameter
Min
Max
Unit
Notes
P1
tPLPH
RP# Pulse Low Time
(If RP# is tied to VCC, this
specification is not
applicable)
RP# is asserted during block erase,
program or lock-bit configuration
operation
25
—
µs
1
RP# is asserted during read
100
—
ns
1
P2
tPHRH
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration
—
100
ns
1,2
P3
tVCCPH
Vcc Power Valid to RP# de-assertion (high)
60
—
µs
—
Notes:
1.
These specifications are valid for all product versions (packages and speeds).
2.
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
Figure 13: AC Input/Output Reference Waveform
Figure 14: Transient Equivalent Testing Load Circuit
Table 15: Test Configuration
Test Configuration
CL (pF)
VCCQ = VCCQMIN
30
Output
Test Points
Input
V
CCQ/2
V
CCQ
0.0
V
CCQ/2
Device
Under Test
C
L
Out



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