JS28F320J3F75 datasheet(39/67 Pages) NUMONYX

39 / 67 page

Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Datasheet

After all user-data is written into the write buffer, issue the confirm command. If a

command other than the confirm command is issued to the device, a command

sequence error occurs and the operation aborts.

Note:

After issuing the confirm command, write-buffer contents are programmed into the

flash memory array. The Status Register indicates a busy status (SR.7 = 0) during

array programming.Issuing the Read Array command to the device while it is actively

programming or erasing causes subsequent reads from the device to output invalid

data. Valid array data is output only after the program or erase operation has finished.

Upon completion of array programming, the Status Register indicates ready (SR.7 = 1).

A full Status Register check should be performed to check for any programming errors,

then cleared by using the Clear Status Register command.

Additional buffered programming operations can be initiated by issuing another setup

command, and repeating the buffered programming bus-cycle sequence. However, any

errors in the Status Register must first be cleared before another buffered

programming operation can be initiated.

9.4

Block Erase Operations

Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation

must be performed (See Section 9.3, “Programming Operations”). Erasing is performed

on a block basis - an entire block is erased each time an erase command sequence is

issued. Once a block is fully erased, all addressable locations within that block read as

logical ones (FFFFh for x16 mode, FFh for x8 mode). Only one block-erase operation

can occur at a time, and is not permitted during a program suspend.

To perform a block-erase operation, issue the Block Erase command sequence at the

desired block address. Table 23 shows the two-cycle Block Erase command sequence.

Note:

A block-erase operation requires the addressed block to be unlocked, and a valid

voltage applied to VPEN throughout the block-erase operation. Otherwise, the

operation will abort, setting the appropriate Status Register error bit(s).

The Erase Confirm command latches the address of the block to be erased. The

addressed block is preconditioned (programmed to all zeros), erased, and then verified.

The read mode of the device is automatically changed to Read Status Register mode,

and remains in effect until another read-mode command is issued.

During a block-erase operation, STS and the Status Register indicates a busy status

(SR.7 = 0). Upon completion, STS and the Status Register indicates a ready status

(SR.7 = 1). The Status Register should be checked for any errors, then cleared. If any

errors did occur, subsequent erase commands to the device are ignored unless the

Status Register is cleared.

The only valid commands during a block erase operation are Read Array, Read Device

Information, CFI Query, and Erase Suspend. After the block-erase operation has

completed, any valid command can be issued.

Table 23: Block-Erase Command Bus-Cycles

Command

Setup Write Cycle

Confirm Write Cycle

Address Bus

Data Bus

Address Bus

Data Bus

Block Erase

Block Address

0020h

Block Address

00D0h

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