AMD-766AC datasheet(9/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

3.4

ISA/LPC Bus and Legacy Support Signals

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

BCLK. ISA bus clock. This is the approximately 8 MHz ISA-bus clock.

It is the frequency of PCLK divided by four.

Output VDD3

Func.

EKIRQ1. External keyboard controller IRQ1. This is designed to be

connected to the keyboard controller’s IRQ1 for the internal interrupt

controller logic.

Input

VDD3

Input

Func.

EKIRQ12. External keyboard controller IRQ12 mouse interrupt. This is

designed to be connected to the keyboard controller’s IRQ12 for the

internal interrupt controller logic. See C3A46[10:9] for information on

how the IRQ12 pin and the mouse interrupt are combined.

Input

VDD3

Input

Func.

IOCHK#. ISA bus IO channel check signal. The assertion of this signal

controls PORT61[IOCHK].

Input-

VDD3

IOCHRDY. ISA bus IO channel ready signal. This is deasserted by ISA

bus slaves to extend the duration of the cycle.

Input-

VDD3

3-state 3-state 3-state

IOR#. ISA bus IO read signal.

Output VDD3

High

IOW#. ISA bus IO write signal.

Output VDD3

High

IRQ[11:9,7:3]. ISA bus interrupt request signals.

REQ[7:0]#. PCI bus master request pins (alternate function to IRQ[11:9,

7:3]; selected by PMF5). These pins may be used to set PM00[BM_STS].

Input-

VDD3

IRQ12. ISA bus interrupt request 12.

SMBALERT#. SMBus alert (alternate function to IRQ12; selected by

C3A46[10:9]). When enabled to do so, this may be used to generate an

SMI or SCI interrupt associated with the SMBus logic.

USBOC1#. USB over current detect 1 (alternate function to IRQ12;

selected by C3A46[10:9]). When enabled to do so, this may be routed to

the USB block to be a second source of USB port over-current detection.

Input

VDD3

IRQ[15,14]. Input; ISA bus interrupt request signals.

NMPIRQ. Native mode primary IDE port IRQ (alternate function to

IRQ14; selected by C1A08[8]). When C1A08[8] is high, this pin becomes

an active-high, shared interrupt that is logically combined with PIRQA#

such that it may be shared with other PCI devices. This is in support of

native mode as defined by the PCI IDE Controller Specification.

NMSIRQ. Native mode secondary IDE port IRQ (alternate function to

IRQ15; selected by C1A08[10]). When C1A08[10] is high, this pin

becomes an active-high, shared interrupt that is logically combined with

PIRQA# such that it may be shared with other PCI devices. This is in

support of native mode as defined by the PCI IDE Controller

Specification.

Input-

VDD3

ISABIOS. Direct BIOS accesses to the ISA bus versus the LPC bus. The

state of this pin may be accessed in C3A48[ISABIOS]. 1=The ISA bus.

0=The LPC bus.

Input

VDD3

Input

KA20G. Keyboard A20 gate. This is designed to be the gate A20 signal

from the system keyboard controller. It affects A20M#.

Input

VDD3

Input

Func.

KBRC#. Keyboard reset command. This is designed to be the processor

Input

VDD3

Input

Func.

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