AMD-766AC datasheet(63/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

C3A50: Power State Pin Control Register

Configuration space; function 3; offset: 53-50h. Default: 1800_0000h. Read-write.

The bits[23:0] of this register specify the output pins controlled during C2, C3, and POS transitions. Each byte

provides the enables for each low-power states. C2 is specified by bits[7:0], C3 is specified by bits [15:8], and POS is

specified by bits[23:16]. See section 4.6.1.5 for timing details.

Note: The reserved bits in this register are read-write accessible, however they control no hardware.

27:25

APIC_POSEN

Reserved

TTHLOCK

TTH_EN

TTH_RATIO

PITRSM#

CRST_POSEN

SUSP_POSEN

CSLP_POSEN

PSTP_POSEN

CSTP_POSEN

POSEN

DCST_POSEN

ZZ_POSEN

CRST_C3EN

SUSP_C3EN

CSLP_C3EN

PSTP_C3EN

CSTP_C3EN

C3EN

DCST_C3EN

ZZ_C3EN

765

43210

CRST_C2EN

SUSP_C2EN

CSLP_C2EN

PSTP_C2EN

CSTP_C2EN

C2EN

DCST_C2EN

ZZ_C2EN

ZZ_[POS,C3,C2]EN. Enable CACHE_ZZ assertion to the L2 cache during power management. 1=Enable control

of the CACHE_ZZ pin during the specified C2, C3, and POS states. 0=CACHE_ZZ is not asserted. This bit has no

effect if the PMC8 does not select the CACHE_ZZ function.

DCST_[POS,C3,C2]EN. Enable DCSTOP# assertion to the DRAM controller during power management.

1=Enable control of the DCSTOP# pin during the specified C2, C3, and POS states. 0=DCSTOP# is not asserted.

[POS,C3,C2]EN. Enable STPCLK# during power management. 1=Enable control of the STPCLK# pin during the

specified C2, C3, and POS states. 0=STPCLK# is not asserted during C2, C3, and POS. This bit required to be set

for any of the other bits in this register’s byte to function (i.e., if STPCLK# is not asserted for a given power state,

then no other power management control signals are asserted for that power state).

CSTP_[POS,C3,C2]EN. Enable CPUSTOP# assertion to the external PLL during power management. 1=Enable

control of the CPUSTOP# pin during the specified C2, C3, and POS states. 0=CPUSTOP# is not asserted. This bit

has no effect if the PMC6 does not select the CPUSTOP# function.

PSTP_[POS,C3,C2]EN. Enable PCISTOP# assertion to the external PLL during power management. 1=Enable

control of the PCISTOP# pin during the specified C2, C3, and POS states. 0=PCISTOP# is not asserted. This bit

has no effect if the PMC7 does not select the PCISTOP# function.

CSLP_[POS,C3,C2]EN. Enable CPUSLEEP# assertion to the processor during power management. 1=Enable

control of the CPUSLEEP# pin during the specified C2, C3, and POS states. 0=CPUSLEEP# is not asserted. This

bit has no effect if the PMC5 does not select the CPUSLEEP# function.

SUSP_[POS,C3,C2]EN. Enable SUSPEND# assertion during power management. 1=Enable control of the

SUSPEND# pin during the specified C2, C3, and POS states. 0=SUSPEND# is always high. This bit has no effect if

the PMC4 does not select the SUSPEND# function.

CRST_[POS,C3,C2]EN. Enable assertion of CPURST# during transition to FON. 1=Enables assertion of the

CPURST# pin during the transition to FON from the specified C2, C3, and POS states. 0=CPURST# is not asserted

during the specified transition. This bit should not be set unless the corresponding SUSP_[POS,C3,C2]EN bit is set

(i.e., processor resets are only allowed if SUSPEND# gets asserted).

PITRSM#. Enable the PIT to generate interrupts during POS. 1=Legacy PIT does not generate IRQ0 while in POS,

starting from the time that the command to enter POS is sent to PM04. This is necessary to prevent timer-tick

interrupts from resuming the system while in POS. 0=PIT generates IRQ0 while in POS.

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