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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AMD-766AC датащи(PDF) 32 Page - Advanced Micro Devices |
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AMD-766AC датащи(HTML) 32 Page - Advanced Micro Devices |
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32 / 96 page  Preliminary Information 23167B – March 2001 AMD-766 TM Peripheral Bus Controller Data Sheet 32 Fixed address spaces. Port(s) Mnemonic Type Function 00-0F PORTxx IO mapped Slave DMA controller 20-21 PORTxx IO mapped Master interrupt controller 40-43 PORTxx IO mapped Programmable interval timer 60, 64 PORTxx IO mapped USB keyboard emulation address 61 PORT61 IO mapped AT Compatibility Register 70-73 RTCxx IO mapped Real-time clock and CMOS RAM 80-8F PORTxx IO mapped DMA page registers 92 PORT92 IO mapped System control register A0-A1 PORTxx IO mapped Slave interrupt controller C0-DF PORTxx IO mapped Master DMA controller F0-F1 PORTxx IO mapped Floating point error control 170-177, 376 PORTxxx IO mapped Secondary IDE drives (not used when in native mode) 1F0-1F7, 376 PORTxxx IO mapped Primary IDE drives (not used when in native mode) 4D0-4D1 PORT4D0 IO mapped EISA-defined level-triggered interrupt control registers CF9 PORTCF9 IO mapped System reset register FEC0_0000 to FEC0_001F IOAxx Memory mapped IOAPIC register set Relocatable address spaces. Base address register Mnemonic Type Size (bytes) Function C1A10 None IO mapped 8 Pointer to primary port IDE command space C1A14 None IO mapped 4 Pointer to primary port IDE control space C1A18 None IO mapped 8 Pointer to secondary port IDE command space C1A1C None IO mapped 4 Pointer to secondary port IDE control space C1A20 IBMx IO mapped 16 IDE controller bus master control registers C3A58 PMxx IO mapped 256 System management IO register space C4A10 USBxxx Memory mapped 4K USB IO register space Note: C1A10, C1A14, C1A18, and C1A20 are only used when the IDE controller is in native mode as specified by C1A08. The following are register behaviors found in the register descriptions. Type Description Read or read only Capable of being read by software. Read only implies that the register cannot be written to by software. Write Capable of being written by software. Set by hardware Register bit is set high hardware. Write 1 to clear Software must write a 1 to the bit in order to clear it. Writing a 0 to these bits has no effect. Write 1 only Software may set the bit high by writing a 1 to it. However subsequent writes of 0 have no effect. RESET# must be asserted in order to clear the bit. Write once After RESET#, these registers may be written to once. After they are written, they become read only until the next RESET# assertion. |
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