AMD-766AC datasheet(64/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

TTH_RATIO. Thermal throttling duty cycle. These specify the duty cycle of the STPCLK# signal to the processor

when the system is in thermal throttling mode (initiated by the THERM# pin when enabled by TTH_EN). The field

is encoded as follows:

RATIO bits

Description

RATIO bits

Description

000b

Reserved.

100b

50.0% STPCLK# active.

001b

87.5% STPCLK# active.

101b

37.5% STPCLK# active.

010b

75.0% STPCLK# active.

110b

25.0% STPCLK# active.

011b

62.5% STPCLK# active.

111b

12.5% STPCLK# active.

TTH_EN. Thermal throttling enable. 1=When THERM# is asserted, thermal throttling (duty cycle specified by

TTH_RATIO) is enabled. Thermal throttling has priority over normal throttling (see PM10); however, it is disabled

if the system is in C2, C3, POS, STR, STD, or SOFF. 0=Thermal throttling disabled.

TTHLOCK. Thermal throttling lock. Write 1 only. 1=Writes to TTH_EN and TTH_RATIO are disabled. Once

set, this bit cannot be cleared by software. It is cleared by PCIRST#. Note: TTH_EN and TTH_RATIO are allowed

to change during the write command that sets TTHLOCK high.

APIC_POSEN. APIC interrupt message bus PICCLK enable during POS state. 1=PICCLK continues operation

during the POS state. 0=PICCLK is driven low after the stop-grant cycle while going into the POS suspend state.

C3A54: PCI IRQ Edge-Or-Level Select Register

Configuration space; function 3; offset: 54h. Default: 00h. Read-write.

7:4

321

Reserved

EDGEPID

EDGEPIC

EDGEPIB

EDGEPIA

EDGEPI[D,C,B,A]. Edge triggered interrupt selects for PCI interrupts. Each of these controls the corresponding

PCI interrupt pin, PIRQ[D,C,B,A]#, polarity in the interrupt routing logic (see section 4.3.4.1 for details). 0=The

PIRQ[D,C,B,A]# signals are assumed to be active low and level triggered. 1=The signals are assumed to be active

low and edge triggered such that the falling edge of the external signals results in rising edges to the PIC. Note:

When these bits are high, the corresponding serial IRQ PCI interrupts are disabled.

C3A56: PCI IRQ Routing Register

Configuration space; function 3; offset: 57-56h. Default: 0000h. Read-write.

15:12

11:8

7:4

3:0

PIRQD# Select

PIRQC# Select

PIRQB# Select

PIRQA# Select

PIRQ[D,C,B,A]# Selects. These map the PCI IRQ pins to the internal ISA-bus-compatible interrupt controller (see

section 4.3.4.1 for details). The fields are encoded as follows:

PIRQ[D,C,B,A]# Selects

Selected IRQ

PIRQ[D,C,B,A]# Selects

Selected IRQ

None

Reserved

IRQ1

IRQ9

Reserved

IRQ10

IRQ3

IRQ11

IRQ4

IRQ12

IRQ5

Reserved

IRQ6

IRQ14

IRQ7

IRQ15

C3A58: System Management IO Space Pointer

Configuration space; function 3; offset: 5B-58h. Default: 0000_DD01h.

31:16

15:8

7:0

Reserved

PMBASE

PMBLSB

PMBASE. Read-write. Specifies PCI address bits[15:8] of the 256-byte block of IO-mapped registers used for

system management (address space PMxx). Access to this address space is enabled by C3A41[PMIOEN].

PMBLSB. Read only. These bits are fixed in their default state.

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