AD1986ABSTZ datasheet(29/56 Pages) AD

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AD1986A

Rev. 0 | Page 29 of 56

GENERAL-PURPOSE (REGISTER 0x20)

This register should be read before writing to generate a mask for only the bit(s) that need to be changed.

Reg

Name

D15

D14

D13

D12

D11

D10

Default

0x20

General-

Purpose

DRSS1

DRSS0

MIX

LPBK

0x0000

Table 87.

Function

Default

LPBK

(Loop-

Back

Control)

This bit enables the digital internal loop back from the ADC to the front DAC. This feature is normally used for

testing and troubleshooting. See LBKS bit in Register 0x74 for changing the loop back path to use the

SURROUND or CENTER/LFE DACs.

Default:

disabled

(0x0)

(MIC

Select)

Used in conjunction with OMS [2:0] (0x74 D10:08]), 2CMIC (0x76 D06) and MMIX (0x7A D02). Selects which MIC

input goes into the ADC0 record selector’s MIC channel inputs. When set, this bit swaps the left and right

channels. Selects mono output audio source.

MIX

Mono Output Connection

MIX—Connected to the mono mixer output.

Default

MIX

(Mono

Output

Select)

MIC—Connected to the left channel of the MIC selector and swap.

The DRSS bits specify the slots for the n+1 sample outputs. PCM L (n+1) and PCM R (n+1) data are by default

provided in output Slots 10 and 11.

DRSS [1:0]

Function

PCM L, R (n+1) data is on Slots 10 and 11

Default

PCM L, R (n+1) data is on Slots 7 and 8

DRSS [1:0]

(Double

Rate Slot

Select)

Reserved

Reserved.

Default: 0

AUDIO INT AND PAGING (REGISTER 0x24)

This register controls the audio interrupt and register paging mechanisms.

Reg

Name

D15

D14

D13

D12

D11

D10

Default

0x24

Audio Int and

Paging

PG3

PG2

PG1

PG0

0xxx00

Table 88.

Function

This register is used to select a descriptor of 16 word pages between Registers 0x60 to 0x6F. A value of 0x0 is used to

select vendor-specific space to maintain compatibility with AC ’97 Revision 2.2 vendor specific registers. System

software can determine implemented pages by writing the page number and reading the value back. If the value read

back does not match the value written, the page is not implemented. All implemented pages must be in consecutive

order (that is, Page 0x2 cannot be implemented without Page 0x1).

PG [3:0]

Addressing Page Selection

Default

000 (Page 0)

Page 0 (vendor) registers

Default

001 (Page 1)

Page ID 01, registers defined in AC ’97, Revision 2.3

PG [3:0]

(Page Selector

(Read/Write))

Page 0x–0xF

Reserved

Software should not unmask the interrupt unless the AC ’97 controller ensures that no conflict is possible with modem

Slot 12—GPI functionality. AC ’97 Revision 2.2-compliant controllers will not likely support audio codec interrupt

infrastructure. In that case, software can poll the interrupt status after initiating a sense cycle and waiting for sense

cycle max delay (defined by software) to determine if an interrupting event has occurred.

Interrupt Mask Status

Interrupt generation is masked

Default

(Interrupt Enable

(Read/Write))

Interrupt generation is unmasked

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