AD1986ABSTZ datasheet(30/56 Pages) AD

30 / 56 page

AD1986A

Rev. 0 | Page 30 of 56

Function

Writing a 1 to this bit causes a sense cycle start if supported. If a sense cycle is in progress, writing a 0 to this bit will

abort the sense cycle. The data in the sense result register (0x6A, Page 01) can or can not be valid, as determined by

the IV bit.

Read

Write

Sense cycle completed (or not initiated)

Default

Aborts sense cycle (if in

process)

Sense cycle still in process

Initiate sense cycle

(Sense Cycle

(Read/Write))

These bits will indicate the cause(s) of an interrupt. This information should be used to service the correct interrupting

event(s). If the Interrupt Status (Bit I4) is set, one or both of these bits must be set to indicate the interrupt cause.

Hardware will reset these bits back to zero when the interrupt status bit is cleared.

Interrupt Status

Sense status has not changed (did not cause interrupt). Default

Sense cycle completed or new sense information is available

GPIO status change did not cause interrupt

I [3:2]

(

Interrupt Cause

(RO))

GPIO status change caused interrupt

Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt

enable (I0) status. An interrupt in the GPI in Slot 12 in the AC link will follow this bit change when interrupt enable (I0)

is unmasked. If this bit is set, one or both of I3 or I2 must be set to indicate the interrupt cause.

Read

Write

Interrupt clear

Default

No operation

(Interrupt Status

(Read/Write))

Interrupt generated

Clears interrupt

Reserved.

Default: 0

POWER-DOWN CTRL/STAT (REGISTER 0x26)

The ready bits are read only; writing to REF, ANL, DAC, and ADC has no effect. These bits indicate the status for the AD1986A

subsections. If the bit is 1 then that subsection is ready.‘Ready’ is defined as the subsection able to perform in its nominal state.

Reg

Name

D15

D14

D13

D12

D11

D10

Default

0x26

Power-

Down

Ctrl/Stat

EAPD

PR6

PR5

PR4

PR3

PR2

PR1

PR0

REF

ANL

DAC

ADC

0x000x

Table 89.

ADC

ADC Status

ADC not ready

ADC sections ready to transmit data

ADC (RO)

(ADC Section

Status (RO))

DAC

Front DAC Status

ADC not ready

ADC (RO)

((Front DAC

Status (RO))

ADC sections ready to transmit data

ANL

Analog Status

Analog amplifiers, attenuators, and mixers not ready

ANL (RO)

(Analog

Amplifiers,

Attenuators and

Mixers Status

(RO))

Analog amplifiers, attenuators, and mixers ready

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