AD1986ABSTZ datasheet(32/56 Pages) AD

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AD1986A

Rev. 0 | Page 32 of 56

Description

Setting

Function

CDAC (RO)

PCM CENTER DAC: read only

= 1

PCM center DAC supported

SDAC (RO)

PCM Surround DAC: read only

= 1

CM Surround DACs supported

LDAC (RO)

PCM LFE DAC: read only

= 1

PCM LFE DAC supported

AMAP (RO)

Slot DAC mappings: read only

= 1

Codec ID based slot/DAC mappings

REV [1:0] (RO)

AC97 version: read only

= 10

Codec is AC ’97, Revision 2.3-compliant

ID [1:0] (RO)

Codec configuration: read only

= 00

Primary AC ‘97

Reserved

Default: 0

EXT’D AUDIO STAT/CTRL (REGISTER 0x2A)

The extended audio status and control register is a read/write register that provides status and control of the extended audio features.

Reg

Name

D15

D14

D13

D12

D11

D10

Default

0x2A

Ext’d Audio Stat/Ctrl

PRK

PRJ

PRI

SPCV

LDAC

SDAC

CDAC

SPSA1

SPSA0

SPDIF

DRA

VRA

0x0xx0

Table 91.

Function

Enables variable rate audio mode. Enables sample rate registers and SLOTREQ signaling.

VRA

VRA State

Default

Disabled, sample rate 48 kHz for all ADCs and DACs

Default

VRA

(Variable Rate

Audio)

Enabled, ADCs and DACs can be set to variable sample rates

DRA = 1. Enables double-rate audio mode in which data from PCM L and PCM R in Output Slots 3 and 4 is used in

conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the

PCM front sample rate control register. When using the double rate audio, only the front DACs are supported and all other

DACs (surround, center, and LFE) are automatically powered down. The slot that contains the additional data is

determined by the DRSS [1:0] bits (0x20 D [11:10]). Note that DRA can be used without VRA, in which case the converter

rates are forced to 96 kHz if DRA = 1.

DRA

DRA State

Default

Disabled, DACs sample at the programmed rate

Default

DRA

(Double Rate

Audio)

Enabled, DACs sample at twice (2×) the programmed rate

SPDIF transmitter subsystem enable/disable bit (read/write).

This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set

high, if the SPDIF pin (48) is pulled down at power-up enabling the codec transmitter logic. If the SPDIF pin is floating or

pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF

transmitter is not available. This bit must always be read back, to verify that the SPDIF transmitter is actually enabled.

SPDIF

Function

Disables the S/PDIF transmitter

Default

Enables the S/PDIF transmitter

SPDIF

AC '97 Revision 2.2 AMAP-compliant default SPDIF slot assignments.

SPSA [1:0]

S/PDIF Slot Assignment

3 and 4

Default

7 and 8

6 and 9

SPSA [1:0]

(SPDIF Slot

Assignment

Bits:

(Read/Write))

10 and 11

CDAC

Center DAC Status

Center DAC not ready

Center DAC section ready to receive data

Surround DAC not ready

CDAC (RO)

(Center DAC

Status)

Surround DAC section ready to receive data

LDAC

LFE DAC Status

LFE DAC not ready

LDAC (RO)

(LFE DAC

Status)

LFE DAC section ready to receive data

SPCV (RO)

Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed

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