Chip Errata

DSP56366 Digital Signal Processor

Mask:2J26D

DSP56366 Errata

366CE2J26D_0_0

NG 11/12/01 pg. 12 of 25

 1997 -2001, Motorola

ES129

Description (added 7/5/2000)

If either HDM1 or HDM0 in the HCR register is set, the value of bits 6 and 5 of

the ICR register should reflect the value of HDM[1–0], respectively. Instead, both

ICR bits reflect DM1. The Host DMA functionality is correct, only the value read

from the ICR register is wrong.

Workaround:

To determine the Host DMA operating mode, read the HDM[2-0] bits in the HCR

register.

2J26D

ES130

Description (added 7/5/2000):

If the DMA writes to HTX, the HTDE status flag is not set immediately after the

data is transferred to the RXH:RXM:RXL registers. HTDE will be set only when

one of the following conditions occurs:

1) The external host accesses one of the HDI08 registers.

2) The 56300 core accesses one of the on-chip peripherals.

3) The DMA reads HRX.

No data is lost.

Workaround: There is none. This bug introduces more lattency in the assertion of

the next DMA transfer request.

2J26D

ES132

Description (added 6/18/2001):

For operating frequencies above 90 MHz, if both the DMA channel and the core

simultaneously access the same 1/4K page of internal memory (X, Y or program),

improper DMA channel operation may occur.

Workaround:

Avoid simultaneous DMA and core accesses to the same 1/4 K page of internal

memory when operating at frequencies above 90 MHz.

2J26D

Errata

Number

Errata Description

Applies

to Mask

Freescale Semiconductor, Inc.

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