Chip Errata

DSP56366 Digital Signal Processor

Mask:2J26D

DSP56366 Errata

366CE2J26D_0_0

NG 11/12/01 pg. 6 of 25

 1997 -2001, Motorola

ES94

Description (added 8/10/98):

Enabling any DMA channel by software for transferring a block of data (TM=011

in the channel control register) might not work properly.

Workaround:

Triggering of a channel for block transfer by software can be replaced by triggering

of the DMA channel for block transfer by a peripheral (e.g. Timer, SCI etc.) that is

not used while the block of data should be transferred by DMA. This can be done as

follows:

1. Set the DSR, DDR and DCO registers of the DMA channel according to the

application case.

2. Transfer mode of the DMA channel (in the DCR register) should be set to TM =

000 or TM = 100 (See Section 8.1.5.3, 563xx UM).

3. DMA Request Source of the DMA channel should be set according to the chosen

peripheral, which should trigger the DMA channel (see Section 8.1.5.6 56300 UM

and "DMA Request Sources" Table in the CORE CONFIGURATION item of the

563xx UM).

4. All others fields of the DCR register, except the DE bit, should be set according

to the application case.

5. Configure the peripheral to assert its DMA request line;

6. Set DE bit of the DCR register.

Example 1:

Assuming that the SCI is not used while the block of #DCO3 words is transferred

by DMA channel 3, the SCI Transmit Data (TDRE = 1, DRS[4:0] = 01111) trigger

can be used instead of a software trigger for channel 3.

1. Initialize DMA channel registers

movep #DSR3,x:M_DSR3

movep #DDR3,x:M_DDR3

movep #DCO3,x:M_DCO3

bset

#0,x:M_PCRE

Now when the DMA channel is enabled, a transfer of the block begins.

2J26D

Errata

Number

Errata Description

Applies

to Mask

Freescale Semiconductor, Inc.

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