Chip Errata

DSP56366 Digital Signal Processor

Mask: 2J26D

Motorola, SPS, Wireless Division

366CE2J26D_0_0

NG 11/12/01 pg. 1 of 25

6501 William Cannon Drive West, Austin, Texas 78735-8598

 1997 -2001 Motorola

General: To prevent the use of instructions or sequences of instructions that do not operate correctly,

use the “lint563” program to identify such cases and use alternative sequences of instructions. This

program is available in the Motorola DSP Tools CLAS package.

Silicon Errata

Errata

Number

Errata Description

Applies

to Mask

ES14

Description (added before 2/18/1996):

When the DMA performs external memory accesses with priority higher than the

core and both continuous mode and interrupt enable bits are set in the channel’s

control register, then the DMA interrupt might not occur if the core performs

external memory access immediately after the enabling (DE = 1) of the DMA

channel.

Workaround: In this scenario any of the following alternatives can be used:

a. Do not set continuous mode.

b. Use dynamic DMA-core priority.

c. Guarantee that the core performs at least two instructions fetched from

internal memory immediately after setting of the DE.

2J26D

ES21

Description (added 4/16/1996):

If the DMA channel performs non-zero wait state data accesses to/from external

memory and the DMA interrupt is enabled, a false interrupt may occur in addition

to the correct one.

Workaround: Ensure that the channel’s DTD status bit in the DSTR register is set

before jumping to the interrupt service routine (i.e., the interrupt is correct only

when DTD is set).

Example:

ORG P:I_DMA2

JSSET #M_DTD2,X:M_DSTR,ISR_ ; ISR_ is interrupt service

routine

; label for DMA channel 2

2J26D

Freescale Semiconductor, Inc.

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