Chip Errata

DSP56366 Digital Signal Processor

Mask:2J26D

DSP56366 Errata

366CE2J26D_0_0

NG 11/12/01 pg. 9 of 25

 1997 -2001, Motorola

ES94

cont.

Note:

Execution of the first two instructions of the sequence must be uninterruptable. The

TE bit of the TCSR0 register must be cleared no later than 33554430 DSP clock

cycles after it is set. Otherwise, an undesirable trigger for the DMA channel is

generated.

Another peripheral can be used for this purpose, but taking into consideration its

specific features.

2J26D

ES95

Description (added 8/15/98):

If more than a single DMA channel is enabled while the DSP stays in the

WAIT processing state, and triggering one of the DMA channels causes an

exit from the WAIT state (See A-6.115, UM), triggering another DMA

channel might cause improper DMA operation.

Workaround:

Assure that only a single DMA channel can be triggered during DSP WAIT

state. If the application cannot guarantee this, other DMA channels should

be disabled before the WAIT processing state is entered and then reenabled

after WAIT state is exited.

2J26D

ES104

Description: (added 11/24/98):

An improper operation may occur when all the following conditions apply:

•

The DMA channel is in a mode that does not automatically clear the DE bit at

the end of the block (DTM[2:0] = 1xx in DCR).

•

This channel is disabled by software (by clearing DE in DCR) while it is trig-

gered for a new transfer.

•

The previous operation is not yet completed.

Workaround:

The DMA channel should be disabled only when it is not triggered for a new

transfer, i.e. when the DACT bit in the DSTR register is cleared.

Note: To perform this operation most efficiently, all other DMA channels should

be disabled.

2J26D

Errata

Number

Errata Description

Applies

to Mask

Freescale Semiconductor, Inc.

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