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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ASM330LHB датащи(PDF) 27 Page - STMicroelectronics |
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ASM330LHB датащи(HTML) 27 Page - STMicroelectronics |
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27 / 131 page  5.3 I²C/I3C coexistence in ASM330LHB In the ASM330LHB, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with I3C timing. The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1 pin when the device is powered up: • INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 15 • INT1 pin connected to Vdd_IO: only I3C active, see Figure 16 Figure 15. I²C and I3C both active (INT1 pin not connected) 1. Address assignment (DAA or ENTDA) must be performed with I²C fast mode plus timing. When the slave is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications. Figure 16. Only I3C active (INT1 pin connected to Vdd_IO) I²C/I3C I3C bus case Dynamic Address Assignment Master resets DA I3C private R/W with and without 7Eh CCC commands Slave event management Error detection and recovery (1) INT1 pin connected to Vdd_IO Only I3C active 1. When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR timing. ASM330LHB I²C/I3C coexistence in ASM330LHB DS13773 - Rev 7 page 27/131 |
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