5.1.5

STAND-BY mode enter/exit

For the transition to standby mode, the generation of a specific pattern at the input of STBY_IN is required,

according to the below description. T0 and T1 are related to Figure 13. The pattern is considered valid if the

timing of T0 and T1 is inside the specified range. Out of range, the pattern detection is not guaranteed.

Figure 13. Standby pattern mechanism

FULL ON state

blank counter

_

T

0

1

2

...

threshold

0

IN PIN

_

STBY

Enable pattern IN

Enable pattern OUT

STAND BY state

ECHO PIN

_

STBY

When a 10 transition on

STBY_IN pin is detected,

the FSM will start to check

the pattern.

When the pattern is

correctly sent,

the activation of the

stand-by mode starts.

When the stand-by mode is

fully reached, the echo is

asserted, and the FSM is able

again to hear theSTBY_IN pin.

STBY_T1

STBY_T0

For a blanking time the

STBY_IN pin will be ignored

to allow the stabilization of

the CPLD.

STBY_T_Blank

After standby mode transition, the STBY_IN pin must be kept at 0 logic level. Bringing it high longer than

STBY_Exit_flt, STPM801 can come back from standby to normal mode. Behavior is reported in Figure 14.

Figure 14. Standby exit sequence

FULL ON state

IN PIN

_

STBY

Enable pattern OUT

Enable pattern IN

STAND BY state

ECHO PIN

_

STBY

When in Stand-by mode, if

STBY_IN pin is high for

STBY_T_Exit, the device

returns in normal mode.

STBY_T_Exit

When the functional mode has been successfully restored,

the echo is deasserted, and the FSM is ready to hear the

STBY_IN pin to return in stand-by mode.

STPM801

STAND-BY behavior in detail

DS13990 - Rev 2

page 25/38