ADAF1080BCPZ datasheet(28/36 Pages) AD

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Data Sheet

ADAF1080

APPLICATIONS INFORMATION

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Rev. 0 | 28 of 36

NONLINEARITY COMPENSATION

The ADAF1080 output has a predictable and repetitive third-order

dependency on the sense field.

This third-order dependency creates an error that can be calibrated

out in the digital domain by implementing the following calculation:

BCALC=

VOUT−VOFFSET + SCOEFF3× VOUT3−VOFFSET

SCALC1

(15)

where:

BCALC is the calculated field measured by the ADAF1080.

VOUT is the measured output of the ADAF1080.

VOFFSET is the output voltage when BSENSE = 0 mT.

SCALC1 is the linear best fit coefficient for the compensated output

voltage using the following equation:

VCALC= VOUT−VOFFSET + SCOEFF3× VOUT3

−VOFFSET

(16)

FLIP COIL AND MEASUREMENT TIMING

Flipping the polarity of the sense field axis of the sensor is achieved

with a rising or falling edge on the FLIP_DRV pin. When an edge is

captured by the ADAF1080, the sensor is not immediately flipped,

as shown in Figure 2, an internal delay (tDELAY) is implemented

to allow for a field measurement to be made before the current

pulse. This delay is to minimize the time where the output of the

sensor is invalid while the flip pulse is applied. Following tDELAY,

the sensor polarity is flipped, while the sensor is being flipped, the

output is invalid for tINVALID. Following tINVALID, a further settling

time, tSETTLING, is required for the output to settle.

tSETTLING is determined by the bandwidth of the amplifier and the

bandwidth of the output anti-alias filter. For large output signals, the

flipping action can also trigger the ripple suppression, loop settling

behavior that has a time constant of approximately 10 μs.

FLIPPING FREQUENCY

Driving the FLIP_DRV pin with a flipping clock signal is recom-

mended to cancel electrical-offset temperature coefficient and elec-

trical-offset lifetime drift of the sensor and its signal chain. The

flipping frequency must be significantly faster than any sense

field variations to correctly capture the electrical offset for the

periodic offset cancellation. Therefore, the flipping functionality of

the ADAF1080 enables measurement free from electrical offset

regardless of the signal chain used in the application.

Flipping and offset calculation can be performed at any time to

achieve best-in-class offset and should be performed when the

electrical offset changes.

FLIP COIL FILTER CONFIGURATION

The AMR sensor requires a short but high-current pulse (IFLIP_ON =

2.4 A for 1.25 µs at TA = 25°C) to flip the sensitivity polarity. Place

a 10 µF capacitor (CFLIP) close to the VDD_FLIP pin to act as a

charge reservoir and to provide the flip pulse. The average current

required for the flipping functionality is as follows:

IFLIP_AVG=1.25 μs×2×IFLIP_ON

tCLK_FLIP_DRV

(17)

where:

IFLIP_ON is the peak current required to flip the sensor.

tCLK_FLIP_DRV is the clock applied at the FLIP_DRV pin, as shown in

Figure 2.

To limit the in-rush current from the supply, use a series resistance

(RFLIP) between the VDD and VDD_FLIP pins. The recommended

values for CFLIP and RFLIP are designed to handle the maximum flip

frequency while limiting the impact on the supply. Table 16 shows

the recommended RFLIP and CFLIP for different flipping frequencies.

Table 16. Recommended RFLIP and CFLIP Values for Different FLIP_DRV

Frequencies

FLIP_DRV Frequency

with 50% Duty Cycle

RFLIP (Ω) CFLIP (µF)

Average Current IFLIP_AVG

with TA = 25°C

Up to 10 Hz

250

Up to 60 µA

Up to 100 Hz

Up to 600 µA

Up to 1000 Hz

Up to 6 mA

CFLIP must be carefully chosen to obtain a capacitance of 10 µF.

Note that the voltage rating and behavior over temperature are

important parameters to ensure that the capacitor has enough

capacitance to supply the flip current required for the flip coil.

VSET VOLTAGE

The VSET voltage can set the output common-mode voltage to half

of the voltage applied to the VSET pin when interfacing with an

ADC. Set the VSET pin to the output voltage range of the ADC to

maximize the usable input range of the ADC.

To ensure a ratiometric measurement, keep the VSET voltage and

the ADC reference voltage proportional to, or equal to, the supply

voltage, VDD.

The typical application diagram shown in Figure 50 and the design

example shown in Figure 58 show a ratiometric measurement

configuration coupled with a 3.3 V and a 5 V ADC, respectively.

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