ADAF1080BCPZ datasheet(26/36 Pages) AD

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Data Sheet

ADAF1080

APPLICATIONS INFORMATION

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Rev. 0 | 26 of 36

RATIOMETRIC OUTPUT CONFIGURATION

The typical applications of the ADAF1080 are designed to be

ratiometric to the supply voltage to prevent any power supply varia-

tions from corrupting the magnetic field measurements. As outlined

previously in the AMR Magnetic Field Sensor section, the output of

the ADAF1080 can be described by the following equation:

VOUT=BSENSE×SDEVICE×VDD5+VSET2 (5)

The typical transfer function of an n-bit ADC can be simplified to the

following equation:

Digital

Code= VINREFADC×2n

(6)

where:

VIN is the voltage applied to the input pin of the ADC.

REFADC is the reference voltage of the ADC.

n is the number of bits of the ADC.

Therefore, by connecting REFADC, VDD, and VSET together, as

shown in Figure 51, the resulting conversion code is equivalent to

the following:

Output

Code=

BSENSE×SDEVICE×VDD5+VDD2

VDD

×2n

=BSENSE×SDEVICE×2n5+2n−1

=BSENSE×SDEVICE×2n5+Midcode

(7)

The converted result is independent of the supply voltage and sup-

ply voltage variation. Due to the ratiometric configuration, precision

measurements can be achieved.

Figure 51. Simplified Schematic of a Ratiometric Configuration

AMPLIFIER SYNCHRONIZATION

The ADAF1080 integrates a precision zero-drift instrumentation

amplifier that removes the offset and low frequency noise (1/f) noise

of the internal circuitry at low frequencies but adds output ripple

at the chopping frequency. This output ripple can be reduced with

an output filter designed to get 20 dB attenuation at the chopping

frequency.

Applications that require a wide bandwidth, or a fast response and

low-phase delay behavior, can synchronize the sampling of the

ADC to the chopping frequency of the ADAF1080 to sample the

output after the output ripple settles. This synchronizing of the ADC

sampling to the chopping frequency enables the use of a wider

bandwidth output filter while keeping the advantages of a zero-drift

instrumentation amplifier.

The synchronization functionality can be enabled by driving the

SYNC_EN pin to VDD and driving the SYNC pin of the ADAF1080

by the convert input (CNV signal) of the ADC. The ADAF1080

internally generates a chopping clock frequency, fCHOP = fSYNC/4.

This chopping clock is internally delayed by 50 ns to ensure that the

chopping action of the amplifier follows the sampling action of the

ADC aligned to the SYNC clock. Therefore, the ADC samples the

fully settled ADAF1080 output before the next chopping action that

triggers an output settling event. See Figure 54 for the system-level

timing diagram.

Figure 52. Synchronization of the ADC Sampling and the Chopping of the

Amplifier

Applications that use a slower ADC sampling clock can generate a

secondary clock from the SYNC clock, as shown in Figure 53.

Figure 53. Generate CNV Signal for the ADC from SYNC Clock

In this case, the SYNC_EN transition from low to high can be used

to indicate which rising edge of the SYNC signal must be used for

the internal chopping signal for the PGIA so that the ADC has the

longest settling time before sampling.

When SYNC_EN goes high, the next rising edge of the SYNC

clock triggers the falling edge of the internal chopping clock after an

internal delay of 50 ns, as shown in Figure 54.

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