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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9654 датащи(PDF) 40 Page - STMicroelectronics |
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L9654 датащи(HTML) 40 Page - STMicroelectronics |
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40 / 59 page  Functional description L9654 40/59 DocID14218 Rev 3 Bit D12 is used to reflect the status of MOSI Read/Write bit. Bit D11 is used to reflect the MOSI bit D11 in the previous command. Bit D10 is used to indicate the deployment condition set in L9654. Refer to Section 4.11.1 for deployment condition bit in MOSI register mode message. Bit D9 and bit D8 are used to report the period of the pulse stretch timer. Bit D1 is used to indicate a "hard-reset" event. This bit is de-asserted ('0'), when POR is detected, RESETB is asserted, RIREF is out-of-range, or GND connection is lost. This bit is set to '1,' after the bit has been read. A soft reset sequence does not affect this bit. Bit D0 is used to report the soft reset sequence status. If valid soft reset sequences are received, bit D0 is set to ‘1.’ Otherwise, bit D0 is set to ‘0.’ When L9654 receives valid soft reset sequences, it sends MISO register mode response containing $0001 in the next SPI transmission. 4.12 MISO register mode response summary Table 24 below summarizes the MISO register mode response of various events and MOSI messages. The MOISO response shown here is the one received in the next valid SPI transmission after each event or MOSI write. Table 25. MISO register mode response summary Event/MOSI message MISO response POR $0004 RESETB $0004 Loss of GND $0004 RIREF out of range $0004 MOSI Write Soft Reset: $AA $1806 MOSI Write Soft Reset: $55 (after $AA) $0007 MOSI Write Pulse Stretch Timer $1X06 |
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