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L9654 датащи(PDF) 17 Page - STMicroelectronics

номер детали L9654
подробное описание детали  Quad squib driver and dual sensor interface ASIC for safety application
PDF  59 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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L9654 датащи(HTML) 17 Page - STMicroelectronics

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DocID14218 Rev 3
17/59
L9654
Electrical specification
58
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1V. V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
All SPI timing is performed with a 200 pF load on MISO unless otherwise noted.
Table 11. SPI timing
No.
Symbol
Parameter
Min
Typ
Max
Unit
-
fop
Transfer frequency
dc
-
5.50
MHz
1
tSCK
SCLK, SCLK_A Period
181
-
-
ns
2
tLEAD
Enable Lead Time
65
-
-
ns
3
tLAG
Enable Lag Time
50
-
-
ns
4
tSCLKHS
SCLK, SCLK_A High Time
65
-
-
ns
5
tSCLKLS
SCLK, SCLK_A Low Time
65
-
-
ns
6
tSUS
MOSI, MOSI_A Input Setup Time
20
-
-
ns
7
tHS
MOSI, MOSI_A Input Hold Time
20
-
-
ns
8
tA
MISO, MISO_A Access Time
-
-
60
ns
9
tDIS
MISO, MISO_A Disable Time (1)
1. Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance on
the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time,
and minimum capacitance on MISO is the worst case for output hold time.
-
-
100
ns
10
tVS
MISO, MISO_A Output Valid Time
-
-
66
ns
11
tHO
MISO, MISO_A Output Hold Time (1)
0
-
-
ns
12
tRO
Rise Time (Design Information)
-
-
30
ns
13
tFO
Fall Time (Design Information)
-
-
30
ns
14
tCSN
CS_A, CS_D, CS_S Negated Time
640
-
-
ns
Figure 5. SPI timing diagram
Figure 6. SPI timing measurement



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