L9654 datasheet(18/59 Pages) STMICROELECTRONICS

18 / 59 page

Functional description

L9654

18/59

DocID14218 Rev 3

Functional description

4.1

Overview

L9654 is an integrated circuit to be used in air bag systems. Its main functions include

deployment of air bags, switched-power sources to satellite sensors, diagnostics of SDM

(Sensing Deployment Module) and arming inputs. L9654 supports 4 deployment loops, 2

satellite-sensor interfaces, and SPI arming inputs.

4.2

Power on reset (POR)

L9654 has a power on reset (POR) circuit, which monitors VDD voltage. When VDD voltage

falls below VRST for longer than or equal to tPOR, all outputs are disabled and all internal

registers are reset to their default condition.

When VDD falls below VRST_L, all outputs are disabled and all internal registers are reset to

their default condition. No delay filter shall be used along with VRST_L threshold.

If VDD voltage falls below VRST for less than tPOR, operation shall not be interrupted.

When VDD rises above VRST, the outputs are enabled. Before VDD reaches VRST, and during

tPOR, none of the outputs turn on.

4.3

RESETB

RESETB pin is active low. The effects of RESETB are similar to those of a POR event,

except during a deployment. When L9654 has a deployment in-progress, it ignores the

RESETB signal.

However, it shall shut itself down as soon as it detects a POR condition. When the

deployment is completed and the RESETB signal is asserted, the device disables its

outputs and resets its internal registers to their default states.

A de-glitch timer is provided to the RESETB pin. The timer protects this pin against spurious

glitches. UT48 neglects the RESETB signal if it is asserted for shorter than tGLITCH.

RESETB has an internal pull-up in case of open circuit. This pin has a de-glitch timer.

4.4

MSG

MSG pin is used to reflect the FIFO status. Its polarity can be configured as well as the

strategy of activation.

Polling mode: Message pin shall be active as soon as one of the 4 FIFO is not empty and

becomes inactive when all 4 FIFO are empty. A microcontroller can periodically monitor the

status of line to understand if there are data received from satellite.

Interrupt mode: Message pin shall be active as soon one of the 4 FIFO is not empty and

becomes inactive when an SPI communication on CS_S interface starts. At the end of the

SPI communication it shall be active if one of the 4 FIFO is not empty, otherwise it shall be

kept inactive. A microcontroller can wait until an edge is present on the line and manage the

data available in the FIFO.

L9654 датащи(PDF) 18 Page - STMicroelectronics

L9654 датащи(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

датащи скачать

ссылки URL