L9654 datasheet(33/59 Pages) STMICROELECTRONICS

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L9654

Functional description

4.11.2

Deployment driver register mode

Table 16. MOSI register mode message definition

Bit

State

Description

D15

Mode bits

D14

D13

Odd Parity

D12

Read (default)

Write

D11

Pulse Stretch Timer Period

Soft Reset Sequence

D10

Deployment Condition: IDEPLOY_12A and

tDEPLOY_2ms

Deployment Condition: IDEPLOY_175A and

tDEPLOY_1ms

Bit

State

Description

Pulse Stretch timer (see table 17)

Soft Reset Sequence

Odd parity check includes all 16 bits. “Don’t care” bit is included in the parity check as well.

When bit D12 is set to ‘0’, device ignores bit D11 through bit D0. This is a read request. In

the next valid CS_D, a register mode response contains the pulse stretch timer register.

If bit D12 is set to ‘1’, bit D11 determines whether the message is intended to program the

duration of the pulse stretch timer or to address the soft reset sequence.

When bit D11 is set to ‘0’, device ignores bit D7 through bit D0. When bit D11 is set to ‘1’, bit

D9 and bit D8 are ignored.

Bit D10 is used to select between two deployment conditions. When bit D10 is set to 0,

deployment events on all channels shall have the deployment current of IDEPL_12A and the

deployment period of tDEPL_2ms. When bit D10 is set to 1, deployment events on all channels

shall have the deployment current of IDEPL_175A and the deployment period of tDEPL_1ms. The

default state of this bit shall be ‘0’.

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