L9654 datasheet(20/59 Pages) STMICROELECTRONICS

20 / 59 page

Functional description

L9654

20/59

DocID14218 Rev 3

Figure 7. SPI block diagram

L9654 has a counter to verify the number of clocks in SCLK and SCLK_A. If the number of

clocks in SCLK is not equal to 16 clocks while CS_D is asserted, it ignores the SPI message

and sends an SPI fault response. If the number of clocks in SCLK is not equal to 64 clocks

while CS_S is asserted, it ignores the entire SPI message and pushes the Bad SPI Bit

Count fault code into the FIFO. If the number of clocks in SCLK_A is not a multiple of 8, it

ignores the command in the arming shift register. Otherwise, the device latches-in the

command.

Figure 8. Arming daisy-chain configuration

Arming SPI interface is based on 8-bit data transfer. The device is capable of receiving a

multiple of 8-bit commands. The first byte of data coming out of MISO_A is the arming

status bits. The subsequent bits are the arming command bits received through MOSI_A

pin. Refer to below figure for an example of arming SPI transmission. This is an example of

arming SPI transmission based on the daisy-chain configuration.

In case of daisy chain connection for arming SPI, device works as following:

All devices IC_1, IC_2, IC_3 shift out data on the falling edge of SCLK_A for the first 8 bits

and shift out data on the rising edge of SCLK_A for the bits after 8 bits. Therefore μP, IC_3,

IC_2 strobe 24 bits on rising edge of SCLK_A:



the first 8 bits are produced (by IC_3, IC_2, IC_1 respectively) on the falling edge of

SCLK_A.



the remaining 16 bits are shifted out on the rising edge.

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