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PCF8545ATT датащи(PDF) 83 Page - NXP Semiconductors |
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PCF8545ATT датащи(HTML) 83 Page - NXP Semiconductors |
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83 / 103 page ![]() PCA8530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2 — 25 September 2014 83 of 103 NXP Semiconductors PCA8530 Automotive 102 x 4 Chip-On-Glass LCD segment driver The other PCA8530 devices are having the OSC pin connected to VDD1, meaning that these devices are ready to receive an external clock signal which is provided by the master device with subaddress A[1:0] = 00. If the master is providing the clock signal to the slave devices, care must be taken that the sending of display enable or disable will be received by both, the master and the slaves at the same time. When the display is disabled, the output from pin CLK is disabled too. The disconnection of the clock may result in a DC component for the display. In cascaded applications that use an external clock, all devices have the OSC pin connected to VDD1 and thus an external CLK being provided for the system (all devices connected to the same external CLK). 15.2.3 Display data The storage of display data is determined by the contents of the device address register (see Section 8.2.3 on page 11). Storage is allowed only when the content of the device address register matches with the hardware device address applied to the pins A0 and A1. If the content of the device address register and the hardware device address do not match, data storage is inhibited but the data pointer is incremented as if data storage had taken place. The hardware device address must not be changed while the device is being accessed on the interface. 15.2.4 Data read Only when the content of the device address register (see Section 8.2.3 on page 11) matches with the hardware device address applied to the pins A0 and A1, the temperature or device status readout (see Section 8.2.7 on page 13) is activated. If the content of the device address register and the hardware device address do not match, the data output pin (SDA or SDO) of the device is in 3-state. With this, bus conflicts and incorrect reading is prevented. |
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